Lines Matching refs:BIT_5
63 #define BIT_5 0x20
226 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
398 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
593 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
614 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
739 #define MBX_5 BIT_5
1253 #define CF_READ BIT_5
1347 #define PO_DISABLE_INCR_REF_TAG BIT_5
1426 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
2504 #define DT_ISP6312 BIT_5
2867 #define DFLG_DEV_FAILED BIT_5