Lines Matching refs:BIT_1
1158 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0;
1735 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb);
1807 BIT_1 | BIT_0, mb);
1824 BIT_1 | BIT_0, mb);
1869 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
1879 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
1946 BIT_3 | BIT_2 | BIT_1 | BIT_0,
1960 BIT_3 | BIT_2 | BIT_1 | BIT_0,
2178 status = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
2252 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
2264 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
2270 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2285 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2294 BIT_1 | BIT_0, &mb[0]);
2300 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
2314 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
2318 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2322 mb[1] = BIT_1; /* Data DMA Channel Burst Enable */
2323 mb[2] = BIT_1; /* Command DMA Channel Burst Enable */
2324 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
2328 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2334 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
2611 status = qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
2665 status = qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
3786 else if (pkt->entry_status & BIT_1)
3806 } else if (pkt->entry_status & BIT_1) { /* FULL flag */
3983 qla1280_mailbox_command(ha, BIT_6 | BIT_3 | BIT_2 | BIT_1 | BIT_0,