Lines Matching refs:DTC_CONTROL_REG
98 #define DTC_CONTROL_REG 0x100 /* rw */
266 NCR5380_write(DTC_CONTROL_REG, CSR_5380_INTR); /* Enable int's */
363 NCR5380_write(DTC_CONTROL_REG, CSR_DIR_READ);
365 NCR5380_write(DTC_CONTROL_REG, CSR_DIR_READ | CSR_INT_BASE);
370 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY)
381 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS))
414 NCR5380_write(DTC_CONTROL_REG, 0);
416 NCR5380_write(DTC_CONTROL_REG, CSR_5380_INTR);
421 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY)
429 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS))