Lines Matching refs:NCR5380_write
125 * NCR5380_write(register, value) - write to the specific register
788 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
789 NCR5380_write(MODE_REG, MR_BASE);
790 NCR5380_write(TARGET_COMMAND_REG, 0);
791 NCR5380_write(SELECT_ENABLE_REG, 0);
1131 NCR5380_write(MODE_REG, MR_BASE);
1132 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1327 NCR5380_write(TARGET_COMMAND_REG, 0);
1333 NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask);
1334 NCR5380_write(MODE_REG, MR_ARBITRATE);
1348 NCR5380_write(MODE_REG, MR_BASE);
1349 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
1362 NCR5380_write(MODE_REG, MR_BASE);
1379 NCR5380_write(MODE_REG, MR_BASE);
1388 NCR5380_write(INITIATOR_COMMAND_REG,
1393 NCR5380_write(MODE_REG, MR_BASE);
1394 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1413 NCR5380_write(MODE_REG, MR_BASE);
1414 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1425 NCR5380_write(OUTPUT_DATA_REG, (hostdata->id_mask | (1 << cmd->device->id)));
1433 NCR5380_write(INITIATOR_COMMAND_REG, (ICR_BASE | ICR_ASSERT_BSY |
1435 NCR5380_write(MODE_REG, MR_BASE);
1443 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1447 NCR5380_write(SELECT_ENABLE_REG, 0);
1456 NCR5380_write(INITIATOR_COMMAND_REG, (ICR_BASE | ICR_ASSERT_DATA |
1499 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
1502 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1508 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
1519 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
1521 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
1584 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
1605 NCR5380_write(OUTPUT_DATA_REG, *d);
1620 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA);
1622 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1625 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1628 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1633 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ACK);
1654 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
1656 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1695 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
1710 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
1713 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN |
1717 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
1778 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
1781 NCR5380_write(MODE_REG, MR_BASE | MR_DMA_MODE | MR_ENABLE_EOP_INTR | MR_MONITOR_BSY);
1796 NCR5380_write(START_DMA_INITIATOR_RECEIVE_REG, 0);
1798 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA);
1799 NCR5380_write(START_DMA_SEND_REG, 0);
1842 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
1844 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN |
1848 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1915 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1942 NCR5380_write(SELECT_ENABLE_REG, 0); /* disable reselects */
1961 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1967 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
2001 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2030 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
2082 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
2087 NCR5380_write(TARGET_COMMAND_REG, 0);
2101 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2103 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
2126 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2142 NCR5380_write(TARGET_COMMAND_REG, 0);
2145 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
2163 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2165 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
2182 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2196 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2246 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
2267 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
2323 NCR5380_write(MODE_REG, MR_BASE);
2339 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_BSY);
2343 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2373 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2430 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2477 /* NCR5380_write(INITIATOR_COMMAND_REG, ICR_ASSERT_ATN); */
2660 NCR5380_write(TARGET_COMMAND_REG,
2663 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST);
2666 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2667 NCR5380_write(MODE_REG, MR_BASE);
2668 NCR5380_write(TARGET_COMMAND_REG, 0);
2669 NCR5380_write(SELECT_ENABLE_REG, 0);