Lines Matching refs:r4
25 stmfd sp!, {r4 - r7, lr}
32 ldmia r0!, {r3, r4, r5, r6}
34 orr r3, r3, r4, lsl #16
35 and r4, r5, lr
36 orr r4, r4, r6, lsl #16
44 LOADREGS(fd, sp!, {r4 - r7, pc})
48 ldmia r0!, {r3, r4, r5, r6}
50 orr r3, r3, r4, lsl #16
51 and r4, r5, lr
52 orr r4, r4, r6, lsl #16
53 stmia r1!, {r3 - r4}
54 LOADREGS(eqfd, sp!, {r4 - r7, pc})
59 ldmia r0!, {r3, r4}
61 orr r3, r3, r4, lsl #16
63 LOADREGS(eqfd, sp!, {r4 - r7, pc})
72 LOADREGS(fd, sp!, {r4 - r7, pc})
79 stmfd sp!, {r4 - r6, lr}
84 ldmia r1!, {r4, r6, ip, lr}
85 mov r3, r4, lsl #16
87 mov r4, r4, lsr #16
88 orr r4, r4, r4, lsl #16
93 stmia r0!, {r3, r4, r5, r6}
96 mov r4, ip, lsr #16
97 orr r4, r4, r4, lsl #16
102 stmia r0!, {r3, r4, ip, lr}
104 LOADREGS(fd, sp!, {r4 - r6, pc})
108 ldmia r1!, {r4, r6}
109 mov r3, r4, lsl #16
111 mov r4, r4, lsr #16
112 orr r4, r4, r4, lsl #16
117 stmia r0!, {r3, r4, r5, r6}
118 LOADREGS(eqfd, sp!, {r4 - r6, pc})
123 ldr r4, [r1], #4
124 mov r3, r4, lsl #16
126 mov r4, r4, lsr #16
127 orr r4, r4, r4, lsl #16
128 stmia r0!, {r3, r4}
129 LOADREGS(eqfd, sp!, {r4 - r6, pc})
137 LOADREGS(fd, sp!, {r4 - r6, pc})