Lines Matching defs:RESET
511 #define RESET BIT(7)
1770 if (hp_int & (FIFO | TIMEOUT | RESET | SCAM_SEL) || bm_status) {
1776 (FIFO | TIMEOUT | RESET | SCAM_SEL));
2047 (BUS_FREE | RESET))) {
2053 else if (p_int & RESET) {
2767 (PHASE | RESET))
2849 while (!(RDW_HARPOON((port + hp_intstat)) & (PHASE | RESET)) &&
3762 while (!(RDW_HARPOON((p_port + hp_intstat)) & (BUS_FREE | RESET)) &&
3782 while (!(RDW_HARPOON((p_port + hp_intstat)) & (BUS_FREE | RESET))) {
3793 if (!(RDW_HARPOON((p_port + hp_intstat)) & (BUS_FREE | RESET))) {
3869 if (RDW_HARPOON((port + hp_intstat)) & RESET) {
3896 (BUS_FREE | ICMD_COMP | ITAR_DISC | RESET))) {
4046 if (!(RDW_HARPOON((port + hp_intstat)) & (BUS_FREE | RESET)))
4089 if (!(RDW_HARPOON((port + hp_intstat)) & (BUS_FREE | RESET)))
4565 WRW_HARPOON(map_addr, RAT_OP); /*RESET ATTENTION */
6170 (RESET | TIMEOUT | SEL | BUS_FREE | AUTO_INT));
6179 (RESET | PROG_HLT | TIMEOUT | AUTO_INT))) {
6182 if (RDW_HARPOON((p_port + hp_intstat)) & RESET)
6193 if (RDW_HARPOON((p_port + hp_intstat)) & (RESET | TIMEOUT)) {
6196 (RESET | TIMEOUT | SEL | BUS_FREE | PHASE));
6501 FPT_default_intena = RESET | RSEL | PROG_HLT | TIMEOUT |