Lines Matching defs:status_reg_value
561 static int twa_check_bits(u32 status_reg_value)
565 if ((status_reg_value & TW_STATUS_EXPECTED_BITS) != TW_STATUS_EXPECTED_BITS)
567 if ((status_reg_value & TW_STATUS_UNEXPECTED_BITS) != 0)
903 static int twa_decode_bits(TW_Device_Extension *tw_dev, u32 status_reg_value)
908 if (status_reg_value & TW_STATUS_PCI_PARITY_ERROR) {
913 if (status_reg_value & TW_STATUS_PCI_ABORT) {
919 if (status_reg_value & TW_STATUS_QUEUE_ERROR) {
927 if (status_reg_value & TW_STATUS_MICROCONTROLLER_ERROR) {
942 u32 status_reg_value, response_que_value;
945 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
947 while (((status_reg_value & TW_STATUS_RESPONSE_QUEUE_EMPTY) == 0) && (count < TW_MAX_RESPONSE_DRAIN)) {
949 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
1221 u32 status_reg_value;
1231 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
1234 if (!(status_reg_value & TW_STATUS_VALID_INTERRUPT))
1244 if (twa_check_bits(status_reg_value)) {
1245 if (twa_decode_bits(tw_dev, status_reg_value)) {
1252 if (status_reg_value & TW_STATUS_HOST_INTERRUPT)
1256 if (status_reg_value & TW_STATUS_ATTENTION_INTERRUPT) {
1271 if (status_reg_value & TW_STATUS_COMMAND_INTERRUPT) {
1292 if (status_reg_value & TW_STATUS_RESPONSE_INTERRUPT) {
1295 while ((status_reg_value & TW_STATUS_RESPONSE_QUEUE_EMPTY) == 0) {
1363 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
1364 if (twa_check_bits(status_reg_value)) {
1365 if (twa_decode_bits(tw_dev, status_reg_value)) {
1477 u32 status_reg_value;
1481 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
1484 if (twa_check_bits(status_reg_value))
1485 twa_decode_bits(tw_dev, status_reg_value);
1487 while ((status_reg_value & flag) != flag) {
1488 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
1490 if (twa_check_bits(status_reg_value))
1491 twa_decode_bits(tw_dev, status_reg_value);
1506 u32 status_reg_value;
1510 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
1513 if (twa_check_bits(status_reg_value))
1514 twa_decode_bits(tw_dev, status_reg_value);
1516 while ((status_reg_value & flag) != 0) {
1517 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
1518 if (twa_check_bits(status_reg_value))
1519 twa_decode_bits(tw_dev, status_reg_value);
1534 u32 status_reg_value;
1547 status_reg_value = readl(TW_STATUS_REG_ADDR(tw_dev));
1549 if (twa_check_bits(status_reg_value))
1550 twa_decode_bits(tw_dev, status_reg_value);
1552 if (((tw_dev->pending_request_count > 0) && (tw_dev->state[request_id] != TW_S_PENDING)) || (status_reg_value & TW_STATUS_COMMAND_QUEUE_FULL)) {