Lines Matching defs:shadow_regs
80 u8 shadow_regs[MAX8660_N_REGS]; /* as chip is write only */
90 u8 reg_val = (max8660->shadow_regs[reg] & mask) | val;
97 max8660->shadow_regs[reg] = reg_val;
110 u8 val = max8660->shadow_regs[MAX8660_OVER1];
140 u8 selector = max8660->shadow_regs[reg];
194 u8 selector = max8660->shadow_regs[MAX8660_MDTV2];
238 u8 val = max8660->shadow_regs[MAX8660_OVER2];
268 u8 selector = (max8660->shadow_regs[MAX8660_L12VCR] >> shift) & 0xf;
375 max8660->shadow_regs[MAX8660_OVER1] = 5;
387 max8660->shadow_regs[MAX8660_ADTV1] =
388 max8660->shadow_regs[MAX8660_ADTV2] =
389 max8660->shadow_regs[MAX8660_SDTV1] =
390 max8660->shadow_regs[MAX8660_SDTV2] = 0x1b;
391 max8660->shadow_regs[MAX8660_MDTV1] =
392 max8660->shadow_regs[MAX8660_MDTV2] = 0x04;
404 max8660->shadow_regs[MAX8660_OVER1] |= 1;
409 max8660->shadow_regs[MAX8660_OVER1] |= 4;
417 max8660->shadow_regs[MAX8660_OVER2] |= 2;
427 max8660->shadow_regs[MAX8660_OVER2] |= 4;