Lines Matching refs:temp_byte
138 u8 temp_byte;
176 temp_byte = (temp_word >> hp_slot) & 0x01;
177 temp_byte |= (temp_word >> (hp_slot + 7)) & 0x02;
179 if (temp_byte != func->presence_save) {
1262 u8 temp_byte;
1289 temp_byte = readb(ctrl->hpc_reg + SLOT_POWER);
1291 writeb(temp_byte, ctrl->hpc_reg + SLOT_POWER);
1410 u8 temp_byte;
1434 temp_byte = readb(ctrl->hpc_reg + SLOT_POWER);
1436 writeb(temp_byte, ctrl->hpc_reg + SLOT_POWER);
1615 u8 temp_byte;
1664 temp_byte = readb(ctrl->hpc_reg + SLOT_SERR);
1665 temp_byte &= ~(0x01 << hp_slot);
1666 writeb(temp_byte, ctrl->hpc_reg + SLOT_SERR);
2257 u8 temp_byte, function, max_functions, stop_it;
2268 rc = pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(func->device, func->function), 0x0E, &temp_byte);
2274 if (temp_byte & 0x80) /* Multi-function device */
2356 u8 temp_byte;
2385 rc = pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &temp_byte);
2389 if ((temp_byte & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
2405 temp_byte = bus_node->base;
2407 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, temp_byte);
2412 temp_byte = bus_node->base + bus_node->length - 1;
2414 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, temp_byte);
2419 temp_byte = 0x40;
2420 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SEC_LATENCY_TIMER, temp_byte);
2423 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_LATENCY_TIMER, temp_byte);
2428 temp_byte = 0x08;
2429 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_CACHE_LINE_SIZE, temp_byte);
2509 temp_byte = io_node->base >> 8;
2510 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_IO_BASE, temp_byte);
2512 temp_byte = (io_node->base + io_node->length - 1) >> 8;
2513 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_IO_LIMIT, temp_byte);
2617 temp_byte = temp_resources.bus_head->base - 1;
2620 rc = pci_bus_write_config_byte (pci_bus, devfn, PCI_SUBORDINATE_BUS, temp_byte);
2640 temp_byte = (hold_IO_node->base) >> 8;
2641 rc = pci_bus_write_config_word (pci_bus, devfn, PCI_IO_BASE, temp_byte);
2659 temp_byte = (io_node->base - 1) >> 8;
2660 rc = pci_bus_write_config_byte (pci_bus, devfn, PCI_IO_LIMIT, temp_byte);
2802 } else if ((temp_byte & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
2914 PCI_INTERRUPT_PIN, &temp_byte);
2919 if (temp_byte && resources->irqs &&
2921 (0x01 << ((temp_byte + resources->irqs->barber_pole - 1) & 0x03)))) {
2923 IRQ = resources->irqs->interrupt[(temp_byte +
2940 rc = cpqhp_set_irq(func->bus, func->device, temp_byte, IRQ);
2946 resources->irqs->interrupt[(temp_byte + resources->irqs->barber_pole - 1) & 0x03] = IRQ;
2947 resources->irqs->valid_INT |= 0x01 << (temp_byte + resources->irqs->barber_pole - 1) & 0x03;
2951 temp_byte = 0x40;
2953 PCI_LATENCY_TIMER, temp_byte);
2956 temp_byte = 0x08;
2958 PCI_CACHE_LINE_SIZE, temp_byte);