Lines Matching refs:cfblk
233 struct i82593_conf_block *cfblk = &znet->i593_init;
235 memset(cfblk, 0x00, sizeof(struct i82593_conf_block));
247 cfblk->fifo_limit = 10; /* = 16 B rx and 80 B tx fifo thresholds */
248 cfblk->forgnesi = 0; /* 0=82C501, 1=AMD7992B compatibility */
249 cfblk->fifo_32 = 1;
250 cfblk->d6mod = 0; /* Run in i82593 advanced mode */
251 cfblk->throttle_enb = 1;
254 cfblk->throttle = 8; /* Continuous w/interrupts, 128-clock DMA. */
255 cfblk->cntrxint = 0; /* enable continuous mode receive interrupts */
256 cfblk->contin = 1; /* enable continuous mode */
259 cfblk->addr_len = ETH_ALEN;
260 cfblk->acloc = 1; /* Disable source addr insertion by i82593 */
261 cfblk->preamb_len = 2; /* 8 bytes preamble */
262 cfblk->loopback = 0; /* Loopback off */
265 cfblk->lin_prio = 0; /* Default priorities & backoff methods. */
266 cfblk->tbofstop = 0;
267 cfblk->exp_prio = 0;
268 cfblk->bof_met = 0;
271 cfblk->ifrm_spc = 6; /* 96 bit times interframe spacing */
274 cfblk->slottim_low = 0; /* 512 bit times slot time (low) */
277 cfblk->slottim_hi = 2; /* 512 bit times slot time (high) */
278 cfblk->max_retr = 15; /* 15 collisions retries */
281 cfblk->prmisc = ((dev->flags & IFF_PROMISC) ? 1 : 0); /* Promiscuous mode */
282 cfblk->bc_dis = 0; /* Enable broadcast reception */
283 cfblk->crs_1 = 0; /* Don't transmit without carrier sense */
284 cfblk->nocrc_ins = 0; /* i82593 generates CRC */
285 cfblk->crc_1632 = 0; /* 32-bit Autodin-II CRC */
286 cfblk->crs_cdt = 0; /* CD not to be interpreted as CS */
289 cfblk->cs_filter = 0; /* CS is recognized immediately */
290 cfblk->crs_src = 0; /* External carrier sense */
291 cfblk->cd_filter = 0; /* CD is recognized immediately */
294 cfblk->min_fr_len = ETH_ZLEN >> 2; /* Minimum frame length */
297 cfblk->lng_typ = 1; /* Type/length checks OFF */
298 cfblk->lng_fld = 1; /* Disable 802.3 length field check */
299 cfblk->rxcrc_xf = 1; /* Don't transfer CRC to memory */
300 cfblk->artx = 1; /* Disable automatic retransmission */
301 cfblk->sarec = 1; /* Disable source addr trig of CD */
302 cfblk->tx_jabber = 0; /* Disable jabber jam sequence */
303 cfblk->hash_1 = 1; /* Use bits 0-5 in mc address hash */
304 cfblk->lbpkpol = 0; /* Loopback pin active high */
307 cfblk->fdx = 0; /* Disable full duplex operation */
310 cfblk->dummy_6 = 0x3f; /* all ones, Default multicast addresses & backoff. */
311 cfblk->mult_ia = 0; /* No multiple individual addresses */
312 cfblk->dis_bof = 0; /* Disable the backoff algorithm ?! */
315 cfblk->dummy_1 = 1; /* set to 1 */
316 cfblk->tx_ifs_retrig = 3; /* Hmm... Disabled */
317 cfblk->mc_all = (!netdev_mc_empty(dev) ||
319 cfblk->rcv_mon = 0; /* Monitor mode disabled */
320 cfblk->frag_acpt = 0; /* Do not accept fragments */
321 cfblk->tstrttrs = 0; /* No start transmission threshold */
324 cfblk->fretx = 1; /* FIFO automatic retransmission */
325 cfblk->runt_eop = 0; /* drop "runt" packets */
326 cfblk->hw_sw_pin = 0; /* ?? */
327 cfblk->big_endn = 0; /* Big Endian ? no... */
328 cfblk->syncrqs = 1; /* Synchronous DRQ deassertion... */
329 cfblk->sttlen = 1; /* 6 byte status registers */
330 cfblk->rx_eop = 0; /* Signal EOP on packet reception */
331 cfblk->tx_eop = 0; /* Signal EOP on packet transmission */
334 cfblk->rbuf_size = RX_BUF_SIZE >> 12; /* Set receive buffer size */
335 cfblk->rcvstop = 1; /* Enable Receive Stop Register */
341 for (i = 0, c = (char *) cfblk; i < sizeof (*cfblk); i++)
347 memcpy(znet->tx_cur, cfblk, sizeof(struct i82593_conf_block));