Lines Matching refs:UW2453_REGWRITE
35 #define UW2453_REGWRITE(reg, val) ((((reg) & 0xf) << 20) | ((val) & 0xfffff))
263 val = UW2453_REGWRITE(1, uw2453_autocal_synth[idx]);
265 val = UW2453_REGWRITE(1, uw2453_std_synth[idx]);
272 UW2453_REGWRITE(2, uw2453_synth_divide[idx]), RF_RV_BITS);
280 return zd_rfwrite_locked(chip, UW2453_REGWRITE(3, val), RF_RV_BITS);
286 UW2453_REGWRITE(0, 0x25f98), /* enter IDLE mode */
287 UW2453_REGWRITE(0, 0x25f9a), /* enter CAL_VCO mode */
288 UW2453_REGWRITE(0, 0x25f94), /* enter RX/TX mode */
289 UW2453_REGWRITE(0, 0x27fd4), /* power down RSSI circuit */
306 UW2453_REGWRITE(7, uw2453_txgain[int_value]), RF_RV_BITS);
356 UW2453_REGWRITE(4, 0x2b), /* configure reciever gain */
357 UW2453_REGWRITE(5, 0x19e4f), /* configure transmitter gain */
358 UW2453_REGWRITE(6, 0xf81ad), /* enable RX/TX filter tuning */
359 UW2453_REGWRITE(7, 0x3fffe), /* disable TX gain in test mode */
363 UW2453_REGWRITE(0, 0x25f9c), /* 5d01 cal_fil */
366 UW2453_REGWRITE(1, 0x47),
367 UW2453_REGWRITE(2, 0x999),
370 UW2453_REGWRITE(3, 0x7602),
373 UW2453_REGWRITE(3, 0x46063),
489 r = zd_rfwrite_locked(chip, UW2453_REGWRITE(0, 0x25f94), RF_RV_BITS);
508 r = zd_rfwrite_locked(chip, UW2453_REGWRITE(0, 0x25f90), RF_RV_BITS);