Lines Matching refs:FIELD32
145 #define MAC_CSR0_REVISION FIELD32(0x0000000f)
146 #define MAC_CSR0_CHIPSET FIELD32(0x000ffff0)
155 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
156 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
157 #define MAC_CSR1_HOST_READY FIELD32(0x00000004)
163 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
164 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
165 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
166 #define MAC_CSR2_BYTE3 FIELD32(0xff000000)
177 #define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
178 #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
179 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
185 #define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
186 #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
187 #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
188 #define MAC_CSR4_BYTE3 FIELD32(0xff000000)
202 #define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
203 #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
204 #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
210 #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
222 #define MAC_CSR8_SIFS FIELD32(0x000000ff)
223 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
224 #define MAC_CSR8_EIFS FIELD32(0xffff0000)
234 #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
235 #define MAC_CSR9_CWMIN FIELD32(0x00000f00)
236 #define MAC_CSR9_CWMAX FIELD32(0x0000f000)
237 #define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
251 #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
252 #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
253 #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
254 #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
263 #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
264 #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
265 #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
266 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
272 #define MAC_CSR13_BIT0 FIELD32(0x00000001)
273 #define MAC_CSR13_BIT1 FIELD32(0x00000002)
274 #define MAC_CSR13_BIT2 FIELD32(0x00000004)
275 #define MAC_CSR13_BIT3 FIELD32(0x00000008)
276 #define MAC_CSR13_BIT4 FIELD32(0x00000010)
277 #define MAC_CSR13_BIT5 FIELD32(0x00000020)
278 #define MAC_CSR13_BIT6 FIELD32(0x00000040)
279 #define MAC_CSR13_BIT7 FIELD32(0x00000080)
280 #define MAC_CSR13_BIT8 FIELD32(0x00000100)
281 #define MAC_CSR13_BIT9 FIELD32(0x00000200)
282 #define MAC_CSR13_BIT10 FIELD32(0x00000400)
283 #define MAC_CSR13_BIT11 FIELD32(0x00000800)
284 #define MAC_CSR13_BIT12 FIELD32(0x00001000)
295 #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
296 #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
297 #define MAC_CSR14_HW_LED FIELD32(0x00010000)
298 #define MAC_CSR14_SW_LED FIELD32(0x00020000)
299 #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
300 #define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
328 #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
329 #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
330 #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
331 #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
332 #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
333 #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
334 #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
335 #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
336 #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
337 #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
338 #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
339 #define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
340 #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
341 #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
347 #define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
348 #define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
349 #define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
350 #define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
351 #define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
352 #define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
353 #define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
354 #define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
360 #define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
361 #define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
362 #define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
363 #define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
364 #define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
365 #define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
366 #define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
367 #define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
373 #define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
374 #define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
375 #define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
376 #define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
377 #define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
378 #define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
379 #define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
380 #define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
390 #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
391 #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
392 #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
393 #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
394 #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
395 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
396 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
397 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
398 #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
399 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
415 #define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
416 #define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
417 #define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
418 #define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
424 #define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
425 #define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
426 #define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
427 #define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
437 #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
438 #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
439 #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
440 #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
441 #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
442 #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
458 #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
464 #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
485 #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
486 #define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
492 #define PHY_CSR1_RF_RPI FIELD32(0x00010000)
507 #define PHY_CSR3_VALUE FIELD32(0x000000ff)
508 #define PHY_CSR3_REGNUM FIELD32(0x00007f00)
509 #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
510 #define PHY_CSR3_BUSY FIELD32(0x00010000)
521 #define PHY_CSR4_VALUE FIELD32(0x00ffffff)
522 #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
523 #define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
524 #define PHY_CSR4_PLL_LD FIELD32(0x40000000)
525 #define PHY_CSR4_BUSY FIELD32(0x80000000)
531 #define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
537 #define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
552 #define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
553 #define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
554 #define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
555 #define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
556 #define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
557 #define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
558 #define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
559 #define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
560 #define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
561 #define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
562 #define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
563 #define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
564 #define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
565 #define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
566 #define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
567 #define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
573 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
574 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
575 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
576 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
577 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
578 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
579 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
580 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
594 #define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001)
595 #define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002)
596 #define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004)
597 #define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008)
603 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
604 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
605 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
606 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
607 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
608 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
609 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
610 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
620 #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
621 #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
627 #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
628 #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
634 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
635 #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
641 #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
647 #define STA_CSR4_TX_NO_RETRY_COUNT FIELD32(0x0000ffff)
648 #define STA_CSR4_TX_ONE_RETRY_COUNT FIELD32(0xffff0000)
654 #define STA_CSR4_TX_MULTI_RETRY_COUNT FIELD32(0x0000ffff)
655 #define STA_CSR4_TX_RETRY_FAIL_COUNT FIELD32(0xffff0000)
665 #define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
666 #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
698 #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
699 #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
700 #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
701 #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
711 #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
712 #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
713 #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
714 #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
724 #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
725 #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
726 #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
727 #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
735 #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
736 #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
744 #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
745 #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
787 #define RF3_TXPOWER FIELD32(0x00003e00)
792 #define RF4_FREQ_OFFSET FIELD32(0x0003f000)
940 #define TXD_W0_BURST FIELD32(0x00000001)
941 #define TXD_W0_VALID FIELD32(0x00000002)
942 #define TXD_W0_MORE_FRAG FIELD32(0x00000004)
943 #define TXD_W0_ACK FIELD32(0x00000008)
944 #define TXD_W0_TIMESTAMP FIELD32(0x00000010)
945 #define TXD_W0_OFDM FIELD32(0x00000020)
946 #define TXD_W0_IFS FIELD32(0x00000040)
947 #define TXD_W0_RETRY_MODE FIELD32(0x00000080)
948 #define TXD_W0_TKIP_MIC FIELD32(0x00000100)
949 #define TXD_W0_KEY_TABLE FIELD32(0x00000200)
950 #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
951 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
952 #define TXD_W0_BURST2 FIELD32(0x10000000)
953 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
961 #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
962 #define TXD_W1_AIFSN FIELD32(0x000000f0)
963 #define TXD_W1_CWMIN FIELD32(0x00000f00)
964 #define TXD_W1_CWMAX FIELD32(0x0000f000)
965 #define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
966 #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
967 #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
972 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
973 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
974 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
975 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
980 #define TXD_W3_IV FIELD32(0xffffffff)
985 #define TXD_W4_EIV FIELD32(0xffffffff)
994 #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
995 #define TXD_W5_PACKET_ID FIELD32(0x0000ff00)
996 #define TXD_W5_TX_POWER FIELD32(0x00ff0000)
997 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
1008 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1009 #define RXD_W0_DROP FIELD32(0x00000002)
1010 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
1011 #define RXD_W0_MULTICAST FIELD32(0x00000008)
1012 #define RXD_W0_BROADCAST FIELD32(0x00000010)
1013 #define RXD_W0_MY_BSS FIELD32(0x00000020)
1014 #define RXD_W0_CRC_ERROR FIELD32(0x00000040)
1015 #define RXD_W0_OFDM FIELD32(0x00000080)
1016 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
1017 #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1018 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1019 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1026 #define RXD_W1_SIGNAL FIELD32(0x000000ff)
1027 #define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
1028 #define RXD_W1_RSSI_LNA FIELD32(0x00006000)
1029 #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
1035 #define RXD_W2_IV FIELD32(0xffffffff)
1041 #define RXD_W3_EIV FIELD32(0xffffffff)
1048 #define RXD_W4_ICV FIELD32(0xffffffff)
1060 #define RXD_W5_RESERVED FIELD32(0xffffffff)