Lines Matching refs:word
68 const unsigned int word, const u8 value)
81 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
92 const unsigned int word, u8 *value)
108 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
123 const unsigned int word, const u32 value)
141 rt2x00_rf_write(rt2x00dev, word, value);
765 u8 word;
819 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
1275 u32 word;
1278 rt2x00_desc_read(entry_priv->desc, 0, &word);
1280 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1282 rt2x00_desc_read(entry_priv->desc, 0, &word);
1284 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1285 rt2x00_get_field32(word, TXD_W0_VALID));
1293 u32 word;
1296 rt2x00_desc_read(entry_priv->desc, 5, &word);
1297 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1299 rt2x00_desc_write(entry_priv->desc, 5, word);
1301 rt2x00_desc_read(entry_priv->desc, 0, &word);
1302 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1303 rt2x00_desc_write(entry_priv->desc, 0, word);
1305 rt2x00_desc_read(entry_priv->desc, 0, &word);
1306 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1307 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1308 rt2x00_desc_write(entry_priv->desc, 0, word);
1771 u32 word;
1776 rt2x00_desc_read(txd, 1, &word);
1777 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1778 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1779 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1780 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1781 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1782 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1784 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1785 rt2x00_desc_write(txd, 1, word);
1787 rt2x00_desc_read(txd, 2, &word);
1788 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1789 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1790 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1791 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1792 rt2x00_desc_write(txd, 2, word);
1799 rt2x00_desc_read(txd, 5, &word);
1800 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1801 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1803 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1805 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1806 rt2x00_desc_write(txd, 5, word);
1809 rt2x00_desc_read(txd, 6, &word);
1810 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1812 rt2x00_desc_write(txd, 6, word);
1814 rt2x00_desc_read(txd, 11, &word);
1815 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
1817 rt2x00_desc_write(txd, 11, word);
1821 * Writing TXD word 0 must the last to prevent a race condition with
1825 rt2x00_desc_read(txd, 0, &word);
1826 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1827 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1828 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1830 rt2x00_set_field32(&word, TXD_W0_ACK,
1832 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1834 rt2x00_set_field32(&word, TXD_W0_OFDM,
1836 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1837 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1839 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1841 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1843 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1844 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1845 rt2x00_set_field32(&word, TXD_W0_BURST,
1847 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1848 rt2x00_desc_write(txd, 0, word);
2046 u32 word;
2085 rt2x00_desc_read(entry_priv->desc, 0, &word);
2087 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2088 !rt2x00_get_field32(word, TXD_W0_VALID))
2232 u16 word;
2260 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2261 if (word == 0xffff) {
2262 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2263 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2265 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2267 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2268 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2269 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2270 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2271 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2272 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2275 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2276 if (word == 0xffff) {
2277 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2278 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2279 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2280 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
2281 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2282 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2283 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2284 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2285 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2288 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2289 if (word == 0xffff) {
2290 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2292 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2293 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2296 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2297 if (word == 0xffff) {
2298 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2299 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2300 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2301 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2304 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2305 if (word == 0xffff) {
2306 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2307 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2308 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2309 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2311 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2313 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2314 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2316 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2317 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2320 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2321 if (word == 0xffff) {
2322 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2323 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2324 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2325 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2327 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2329 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2330 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2332 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2333 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2346 * Read EEPROM word for configuration.
2414 * eeprom word.