Lines Matching refs:rt2x00dev
67 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
72 mutex_lock(&rt2x00dev->csr_mutex);
78 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
85 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
88 mutex_unlock(&rt2x00dev->csr_mutex);
91 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
96 mutex_lock(&rt2x00dev->csr_mutex);
106 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
112 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
114 WAIT_FOR_BBP(rt2x00dev, ®);
119 mutex_unlock(&rt2x00dev->csr_mutex);
122 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
127 mutex_lock(&rt2x00dev->csr_mutex);
133 if (WAIT_FOR_RF(rt2x00dev, ®)) {
140 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
141 rt2x00_rf_write(rt2x00dev, word, value);
144 mutex_unlock(&rt2x00dev->csr_mutex);
147 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
153 mutex_lock(&rt2x00dev->csr_mutex);
159 if (WAIT_FOR_MCU(rt2x00dev, ®)) {
164 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
166 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, ®);
169 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
172 mutex_unlock(&rt2x00dev->csr_mutex);
178 struct rt2x00_dev *rt2x00dev = eeprom->data;
181 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
193 struct rt2x00_dev *rt2x00dev = eeprom->data;
203 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
241 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
245 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
257 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
259 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
262 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
265 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
266 (led->rt2x00dev->led_mcu_reg & 0xff),
267 ((led->rt2x00dev->led_mcu_reg >> 8)));
269 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
271 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
274 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
275 (led->rt2x00dev->led_mcu_reg & 0xff),
276 ((led->rt2x00dev->led_mcu_reg >> 8)));
283 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
296 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, ®);
299 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
304 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
308 led->rt2x00dev = rt2x00dev;
319 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
341 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®);
360 rt2x00pci_register_multiwrite(rt2x00dev, reg,
374 rt2x00pci_register_read(rt2x00dev, SEC_CSR1, ®);
376 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
381 rt2x00pci_register_read(rt2x00dev, SEC_CSR5, ®);
383 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
406 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®);
411 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
416 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
435 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®);
438 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®);
460 rt2x00pci_register_multiwrite(rt2x00dev, reg,
464 rt2x00pci_register_multiwrite(rt2x00dev, reg,
472 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, ®);
474 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
497 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®);
502 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
506 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®);
511 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
517 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
528 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
539 !rt2x00dev->intf_ap_count);
546 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
549 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
565 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
570 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
574 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
582 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
591 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
596 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
601 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
604 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
606 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
610 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
612 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
614 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
617 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
619 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
621 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
623 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®);
627 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
630 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
637 rt61pci_bbp_read(rt2x00dev, 3, &r3);
638 rt61pci_bbp_read(rt2x00dev, 4, &r4);
639 rt61pci_bbp_read(rt2x00dev, 77, &r77);
641 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
650 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
655 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
664 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
671 rt61pci_bbp_write(rt2x00dev, 77, r77);
672 rt61pci_bbp_write(rt2x00dev, 3, r3);
673 rt61pci_bbp_write(rt2x00dev, 4, r4);
676 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
683 rt61pci_bbp_read(rt2x00dev, 3, &r3);
684 rt61pci_bbp_read(rt2x00dev, 4, &r4);
685 rt61pci_bbp_read(rt2x00dev, 77, &r77);
687 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
689 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
709 rt61pci_bbp_write(rt2x00dev, 77, r77);
710 rt61pci_bbp_write(rt2x00dev, 3, r3);
711 rt61pci_bbp_write(rt2x00dev, 4, r4);
714 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
719 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
727 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
730 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
737 rt61pci_bbp_read(rt2x00dev, 3, &r3);
738 rt61pci_bbp_read(rt2x00dev, 4, &r4);
739 rt61pci_bbp_read(rt2x00dev, 77, &r77);
748 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
755 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
759 rt61pci_bbp_write(rt2x00dev, 77, r77);
760 rt61pci_bbp_write(rt2x00dev, 3, r3);
761 rt61pci_bbp_write(rt2x00dev, 4, r4);
795 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
810 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
812 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
815 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
819 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
821 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, ®);
824 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
826 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
828 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
830 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
831 rt61pci_config_antenna_5x(rt2x00dev, ant);
832 else if (rt2x00_rf(rt2x00dev, RF2527))
833 rt61pci_config_antenna_2x(rt2x00dev, ant);
834 else if (rt2x00_rf(rt2x00dev, RF2529)) {
835 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
836 rt61pci_config_antenna_2x(rt2x00dev, ant);
838 rt61pci_config_antenna_2529(rt2x00dev, ant);
842 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
849 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
852 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
855 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
858 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
862 rt2x00dev->lna_gain = lna_gain;
865 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
873 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
875 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
877 rt61pci_bbp_read(rt2x00dev, 3, &r3);
879 rt61pci_bbp_write(rt2x00dev, 3, r3);
886 rt61pci_bbp_write(rt2x00dev, 94, r94);
888 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
889 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
890 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
891 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
895 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
896 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
897 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
898 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
902 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
903 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
904 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
905 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
910 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
915 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
916 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
917 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
918 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
920 rt61pci_config_channel(rt2x00dev, &rf, txpower);
923 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
928 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
936 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
939 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
948 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, ®);
950 rt2x00dev->beacon_int - 10);
957 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
960 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
962 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
963 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
964 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
966 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
968 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, ®);
973 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
975 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
976 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
977 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
979 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
983 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
988 rt61pci_config_lna_gain(rt2x00dev, libconf);
991 rt61pci_config_channel(rt2x00dev, &libconf->rf,
995 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
997 rt61pci_config_retry_limit(rt2x00dev, libconf);
999 rt61pci_config_ps(rt2x00dev, libconf);
1005 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1013 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
1019 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
1023 static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1027 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
1033 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1036 rt61pci_set_vgc(rt2x00dev, qual, 0x20);
1039 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1048 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1051 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1058 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1068 if (!rt2x00dev->intf_associated)
1075 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
1083 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1091 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
1099 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1112 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1123 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1125 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
1131 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1136 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1155 static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1184 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1194 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
1201 ERROR(rt2x00dev, "Unstable hardware.\n");
1210 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1211 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1212 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1213 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1221 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1223 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1227 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1230 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1233 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, ®);
1240 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1255 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1257 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1260 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1262 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1264 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1312 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1320 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®);
1322 rt2x00dev->tx[0].limit);
1324 rt2x00dev->tx[1].limit);
1326 rt2x00dev->tx[2].limit);
1328 rt2x00dev->tx[3].limit);
1329 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1331 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®);
1333 rt2x00dev->tx[0].desc_size / 4);
1334 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1336 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1337 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®);
1340 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1342 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1343 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®);
1346 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1348 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1349 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®);
1352 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1354 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1355 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®);
1358 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1360 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®);
1361 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1363 rt2x00dev->rx->desc_size / 4);
1365 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1367 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1368 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®);
1371 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1373 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®);
1378 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1380 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®);
1385 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1387 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1389 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1394 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1398 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1402 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1404 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, ®);
1413 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1418 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, ®);
1427 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1432 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, ®);
1439 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1441 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, ®);
1446 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1448 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, ®);
1453 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1455 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1462 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1464 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1466 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1468 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
1470 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1472 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1474 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1477 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1483 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1484 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1485 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1487 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1488 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1489 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1490 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1492 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1494 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1496 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1504 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1505 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1506 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1507 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1514 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
1515 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
1516 rt2x00pci_register_read(rt2x00dev, STA_CSR2, ®);
1521 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1524 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1526 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1529 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1531 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1533 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1538 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1544 rt61pci_bbp_read(rt2x00dev, 0, &value);
1550 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1554 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1561 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1564 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1565 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1566 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1567 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1568 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1569 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1570 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1571 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1572 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1573 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1574 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1575 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1576 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1577 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1578 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1579 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1580 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1581 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1582 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1583 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1584 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1585 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1586 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1587 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1590 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1595 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1605 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1610 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1614 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1617 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1629 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1630 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1632 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®);
1633 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1640 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
1645 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1647 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®);
1656 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1659 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1666 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1667 rt61pci_init_registers(rt2x00dev) ||
1668 rt61pci_init_bbp(rt2x00dev)))
1674 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1676 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1681 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1686 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1689 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1697 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1700 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1708 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®2);
1712 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1719 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1726 retval = rt61pci_enable_radio(rt2x00dev);
1729 rt61pci_disable_radio(rt2x00dev);
1735 rt61pci_toggle_rx(rt2x00dev, state);
1741 rt61pci_toggle_irq(rt2x00dev, state);
1747 retval = rt61pci_set_state(rt2x00dev, state);
1755 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1764 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1804 TXPOWER_TO_DEV(rt2x00dev->tx_power));
1864 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1873 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1875 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1880 rt61pci_write_tx_desc(rt2x00dev, entry->skb, txdesc);
1885 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1891 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
1893 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
1902 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1907 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1916 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1921 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1926 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1929 static void rt61pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1935 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1939 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1944 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1950 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1952 u8 offset = rt2x00dev->lna_gain;
1970 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1981 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2025 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
2039 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2062 rt2x00pci_register_read(rt2x00dev, STA_CSR4, ®);
2071 queue = rt2x00queue_get_queue(rt2x00dev, type);
2096 WARNING(rt2x00dev,
2135 static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2140 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2145 struct rt2x00_dev *rt2x00dev = dev_instance;
2146 u32 reg = rt2x00dev->irqvalue[0];
2147 u32 reg_mcu = rt2x00dev->irqvalue[1];
2159 rt2x00pci_rxdone(rt2x00dev);
2165 rt61pci_txdone(rt2x00dev);
2171 rt2x00pci_register_write(rt2x00dev,
2178 rt61pci_wakeup(rt2x00dev);
2184 rt2x00lib_beacondone(rt2x00dev);
2187 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
2195 struct rt2x00_dev *rt2x00dev = dev_instance;
2203 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu);
2204 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2206 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
2207 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2212 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2216 rt2x00dev->irqvalue[0] = reg;
2217 rt2x00dev->irqvalue[1] = reg_mcu;
2220 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
2228 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2236 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
2238 eeprom.data = rt2x00dev;
2248 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2254 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2257 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2260 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2271 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2272 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2275 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2284 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2285 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2288 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2292 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2293 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2296 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2300 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2301 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2304 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2308 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2309 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2317 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2320 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2324 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2325 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2333 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2339 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2348 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2354 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
2355 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2358 if (!rt2x00_rf(rt2x00dev, RF5225) &&
2359 !rt2x00_rf(rt2x00dev, RF5325) &&
2360 !rt2x00_rf(rt2x00dev, RF2527) &&
2361 !rt2x00_rf(rt2x00dev, RF2529)) {
2362 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2370 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2375 rt2x00dev->default_ant.tx =
2377 rt2x00dev->default_ant.rx =
2384 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2390 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2395 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2397 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2399 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2404 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2407 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2409 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2416 if (rt2x00_rf(rt2x00dev, RF2529) &&
2417 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2418 rt2x00dev->default_ant.rx =
2420 rt2x00dev->default_ant.tx =
2424 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2426 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2435 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2438 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2439 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2441 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2444 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2445 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2448 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2451 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2454 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2457 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2460 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2462 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2465 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2587 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2589 struct hw_mode_spec *spec = &rt2x00dev->spec;
2597 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2602 rt2x00dev->hw->flags =
2608 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2609 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2610 rt2x00_eeprom_addr(rt2x00dev,
2622 rt2x00dev->hw->max_rates = 7;
2623 rt2x00dev->hw->max_rate_tries = 1;
2631 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2639 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
2653 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2660 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2670 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2677 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2682 retval = rt61pci_validate_eeprom(rt2x00dev);
2686 retval = rt61pci_init_eeprom(rt2x00dev);
2693 retval = rt61pci_probe_hw_mode(rt2x00dev);
2701 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2706 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2707 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2709 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2710 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
2715 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2726 struct rt2x00_dev *rt2x00dev = hw->priv;
2750 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2757 rt2x00pci_register_read(rt2x00dev, offset, ®);
2759 rt2x00pci_register_write(rt2x00dev, offset, reg);
2765 rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, ®);
2767 rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2769 rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, ®);
2771 rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2773 rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, ®);
2775 rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2782 struct rt2x00_dev *rt2x00dev = hw->priv;
2786 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, ®);
2788 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, ®);