Lines Matching refs:rt2x00dev
69 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
72 if (!rt2x00_is_soc(rt2x00dev) ||
73 !rt2x00_rt(rt2x00dev, RT2872))
77 if (rt2x00_rf(rt2x00dev, RF3020) ||
78 rt2x00_rf(rt2x00dev, RF3021) ||
79 rt2x00_rf(rt2x00dev, RF3022))
82 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
86 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
91 mutex_lock(&rt2x00dev->csr_mutex);
97 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
105 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
108 mutex_unlock(&rt2x00dev->csr_mutex);
111 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
116 mutex_lock(&rt2x00dev->csr_mutex);
126 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
133 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135 WAIT_FOR_BBP(rt2x00dev, ®);
140 mutex_unlock(&rt2x00dev->csr_mutex);
143 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
148 mutex_lock(&rt2x00dev->csr_mutex);
154 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
161 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
164 mutex_unlock(&rt2x00dev->csr_mutex);
167 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
172 mutex_lock(&rt2x00dev->csr_mutex);
182 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
188 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190 WAIT_FOR_RFCSR(rt2x00dev, ®);
195 mutex_unlock(&rt2x00dev->csr_mutex);
198 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
203 mutex_lock(&rt2x00dev->csr_mutex);
209 if (WAIT_FOR_RF(rt2x00dev, ®)) {
216 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
217 rt2x00_rf_write(rt2x00dev, word, value);
220 mutex_unlock(&rt2x00dev->csr_mutex);
223 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
232 if (rt2x00_is_soc(rt2x00dev))
235 mutex_lock(&rt2x00dev->csr_mutex);
241 if (WAIT_FOR_MCU(rt2x00dev, ®)) {
246 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
250 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
253 mutex_unlock(&rt2x00dev->csr_mutex);
257 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
263 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
271 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
308 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
323 if (rt2x00_is_usb(rt2x00dev)) {
341 if (rt2x00_is_usb(rt2x00dev) &&
342 !rt2x00_rt(rt2x00dev, RT2860) &&
343 !rt2x00_rt(rt2x00dev, RT2872) &&
344 !rt2x00_rt(rt2x00dev, RT3070) &&
363 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
373 rt2800_register_read(rt2x00dev, MAC_CSR0, ®);
380 ERROR(rt2x00dev, "Unstable hardware.\n");
384 if (rt2x00_is_pci(rt2x00dev))
385 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
391 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
397 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
402 rt2800_drv_write_firmware(rt2x00dev, data, len);
408 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®);
415 ERROR(rt2x00dev, "PBF system register not ready.\n");
422 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
423 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
483 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxwi_w2)
493 if (rt2x00dev->rx_status.band == IEEE80211_BAND_2GHZ) {
494 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
497 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
500 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
503 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
512 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
513 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
514 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
563 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
574 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
583 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
585 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
608 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
614 rt2800_register_multiwrite(rt2x00dev, beacon_base,
623 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
633 static void inline rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
644 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
683 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
687 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®);
700 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
702 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
705 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
709 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
712 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
723 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
736 rt2800_register_read(led->rt2x00dev, LED_CFG, ®);
739 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
744 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
747 led->rt2x00dev = rt2x00dev;
758 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
770 rt2800_register_read(rt2x00dev, offset, ®);
787 rt2800_register_write(rt2x00dev, offset, reg);
789 rt2800_register_write(rt2x00dev, offset, 0);
800 rt2800_register_multiwrite(rt2x00dev, offset,
808 rt2800_register_multiwrite(rt2x00dev, offset,
812 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
832 rt2800_register_multiwrite(rt2x00dev, offset,
848 rt2800_register_read(rt2x00dev, offset, ®);
851 rt2800_register_write(rt2x00dev, offset, reg);
856 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
862 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
888 rt2800_register_multiwrite(rt2x00dev, offset,
895 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
901 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
912 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®);
941 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
945 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
954 rt2800_clear_beacon(rt2x00dev,
959 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
965 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
970 rt2800_register_read(rt2x00dev, INT_TIMER_EN, ®);
973 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
982 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
992 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
998 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
1002 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®);
1007 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1009 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
1012 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1014 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1016 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1018 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®);
1020 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1022 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®);
1024 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1026 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
1029 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1033 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1038 rt2800_bbp_read(rt2x00dev, 1, &r1);
1039 rt2800_bbp_read(rt2x00dev, 3, &r3);
1071 rt2800_bbp_write(rt2x00dev, 3, r3);
1072 rt2800_bbp_write(rt2x00dev, 1, r1);
1076 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1083 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1086 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1089 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1092 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1096 rt2x00dev->lna_gain = lna_gain;
1099 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1104 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1106 if (rt2x00dev->default_ant.tx == 1)
1109 if (rt2x00dev->default_ant.rx == 1) {
1112 } else if (rt2x00dev->default_ant.rx == 2)
1148 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1149 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1150 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1151 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1155 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1156 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1157 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1158 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1162 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1163 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1164 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1165 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1168 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1175 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1176 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1178 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1180 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1182 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1184 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1186 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1188 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1190 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1191 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1192 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1194 rt2800_rfcsr_write(rt2x00dev, 24,
1195 rt2x00dev->calibration[conf_is_ht40(conf)]);
1197 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1199 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1202 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1211 if (rt2x00_rf(rt2x00dev, RF2020) ||
1212 rt2x00_rf(rt2x00dev, RF3020) ||
1213 rt2x00_rf(rt2x00dev, RF3021) ||
1214 rt2x00_rf(rt2x00dev, RF3022))
1215 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1217 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1222 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1223 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1224 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1225 rt2800_bbp_write(rt2x00dev, 86, 0);
1228 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1229 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1230 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1232 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1233 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1236 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1238 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1239 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1241 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1244 rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®);
1248 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1253 if (rt2x00dev->default_ant.tx != 1) {
1259 if (rt2x00dev->default_ant.rx != 1) {
1271 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1273 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1275 rt2800_bbp_write(rt2x00dev, 4, bbp);
1277 rt2800_bbp_read(rt2x00dev, 3, &bbp);
1279 rt2800_bbp_write(rt2x00dev, 3, bbp);
1281 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1283 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1284 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1285 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1287 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1288 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1289 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1296 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1310 rt2800_bbp_read(rt2x00dev, 1, &r1);
1312 rt2800_bbp_write(rt2x00dev, 1, r1);
1327 rt2800_register_read(rt2x00dev, offset, ®);
1330 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1366 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1401 rt2800_register_write(rt2x00dev, offset, reg);
1408 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1413 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®);
1418 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1421 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1430 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1432 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®);
1437 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1439 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1441 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®);
1445 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1447 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1451 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1456 rt2800_config_lna_gain(rt2x00dev, libconf);
1459 rt2800_config_channel(rt2x00dev, libconf->conf,
1462 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1464 rt2800_config_retry_limit(rt2x00dev, libconf);
1466 rt2800_config_ps(rt2x00dev, libconf);
1473 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1480 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®);
1485 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1487 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1488 if (rt2x00_rt(rt2x00dev, RT3070) ||
1489 rt2x00_rt(rt2x00dev, RT3071) ||
1490 rt2x00_rt(rt2x00dev, RT3090) ||
1491 rt2x00_rt(rt2x00dev, RT3390))
1492 return 0x1c + (2 * rt2x00dev->lna_gain);
1494 return 0x2e + rt2x00dev->lna_gain;
1497 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1498 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1500 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1503 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1507 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1513 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1515 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1519 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1522 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1528 rt2800_set_vgc(rt2x00dev, qual,
1529 rt2800_get_default_vgc(rt2x00dev) +
1537 int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1544 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
1550 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1552 ret = rt2800_drv_init_registers(rt2x00dev);
1556 rt2800_register_read(rt2x00dev, BCN_OFFSET0, ®);
1561 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1563 rt2800_register_read(rt2x00dev, BCN_OFFSET1, ®);
1568 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1570 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1571 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1573 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1575 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
1582 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1584 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1586 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®);
1589 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1591 if (rt2x00_rt(rt2x00dev, RT3071) ||
1592 rt2x00_rt(rt2x00dev, RT3090) ||
1593 rt2x00_rt(rt2x00dev, RT3390)) {
1594 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1595 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1596 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1597 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1598 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1599 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1601 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1604 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1607 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1609 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1610 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1612 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1613 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1614 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1616 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1617 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1619 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1620 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1621 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1622 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
1624 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1625 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1628 rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®);
1637 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1639 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®);
1643 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1645 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®);
1647 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1648 rt2x00_rt(rt2x00dev, RT2883) ||
1649 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
1655 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1657 rt2800_register_read(rt2x00dev, LED_CFG, ®);
1665 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1667 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1669 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®);
1676 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1678 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®);
1686 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1688 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®);
1699 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1701 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
1712 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1714 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®);
1725 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1727 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®);
1730 !rt2x00_is_usb(rt2x00dev));
1739 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1741 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®);
1752 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1754 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®);
1765 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1767 if (rt2x00_is_usb(rt2x00dev)) {
1768 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1770 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
1780 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1783 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1784 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1786 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®);
1791 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1793 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1802 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®);
1808 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1810 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1816 rt2800_register_write(rt2x00dev,
1821 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1824 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1825 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1831 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
1832 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
1833 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
1834 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
1835 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
1836 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
1837 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
1838 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
1840 if (rt2x00_is_usb(rt2x00dev)) {
1841 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®);
1843 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
1846 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®);
1855 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1857 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®);
1866 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1868 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®);
1877 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1879 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®);
1884 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1891 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®);
1892 rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®);
1893 rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®);
1894 rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®);
1895 rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®);
1896 rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®);
1901 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, ®);
1903 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
1909 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1915 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®);
1922 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1926 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1935 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1936 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1940 rt2800_bbp_read(rt2x00dev, 0, &value);
1946 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1950 int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1957 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1958 rt2800_wait_bbp_ready(rt2x00dev)))
1961 if (rt2800_is_305x_soc(rt2x00dev))
1962 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1964 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1965 rt2800_bbp_write(rt2x00dev, 66, 0x38);
1967 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1968 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1969 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1971 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1972 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1975 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1977 if (rt2x00_rt(rt2x00dev, RT3070) ||
1978 rt2x00_rt(rt2x00dev, RT3071) ||
1979 rt2x00_rt(rt2x00dev, RT3090) ||
1980 rt2x00_rt(rt2x00dev, RT3390)) {
1981 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1982 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1983 rt2800_bbp_write(rt2x00dev, 81, 0x33);
1984 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1985 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1986 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1988 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1991 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1992 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1994 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
1995 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1997 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1999 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2000 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2001 rt2800_bbp_write(rt2x00dev, 92, 0x00);
2003 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2004 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2005 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2006 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2007 rt2800_is_305x_soc(rt2x00dev))
2008 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2010 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2012 if (rt2800_is_305x_soc(rt2x00dev))
2013 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2015 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2016 rt2800_bbp_write(rt2x00dev, 106, 0x35);
2018 if (rt2x00_rt(rt2x00dev, RT3071) ||
2019 rt2x00_rt(rt2x00dev, RT3090) ||
2020 rt2x00_rt(rt2x00dev, RT3390)) {
2021 rt2800_bbp_read(rt2x00dev, 138, &value);
2023 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2029 rt2800_bbp_write(rt2x00dev, 138, value);
2034 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2039 rt2800_bbp_write(rt2x00dev, reg_id, value);
2047 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2057 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2059 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2061 rt2800_bbp_write(rt2x00dev, 4, bbp);
2063 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2065 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2070 rt2800_bbp_write(rt2x00dev, 24, 0);
2073 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2076 rt2800_bbp_read(rt2x00dev, 55, &passband);
2084 rt2800_bbp_write(rt2x00dev, 24, 0x06);
2087 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2090 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2098 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2103 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2107 int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2114 if (!rt2x00_rt(rt2x00dev, RT3070) &&
2115 !rt2x00_rt(rt2x00dev, RT3071) &&
2116 !rt2x00_rt(rt2x00dev, RT3090) &&
2117 !rt2x00_rt(rt2x00dev, RT3390) &&
2118 !rt2800_is_305x_soc(rt2x00dev))
2124 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2126 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2129 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2131 if (rt2x00_rt(rt2x00dev, RT3070) ||
2132 rt2x00_rt(rt2x00dev, RT3071) ||
2133 rt2x00_rt(rt2x00dev, RT3090)) {
2134 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2135 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2136 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2137 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
2138 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2139 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
2140 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2141 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2142 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2143 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2144 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2145 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2146 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2147 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2148 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2149 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2150 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2151 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2152 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
2153 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2154 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2155 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2156 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2157 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
2158 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2159 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2160 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2161 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2162 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2163 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2164 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
2165 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2166 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2167 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
2168 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2169 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2170 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2171 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2172 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2173 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2174 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2175 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
2176 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2177 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
2178 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2179 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2180 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2181 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2182 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2183 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2184 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2185 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2186 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2187 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2188 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2189 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2190 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2191 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2192 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2193 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2194 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2195 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2196 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2197 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2198 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2199 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2200 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2201 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2202 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2203 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2204 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2205 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2206 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2207 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2208 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2209 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2210 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2211 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2212 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2213 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2214 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2215 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2216 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
2217 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2218 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2222 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2223 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
2226 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2227 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2228 rt2x00_rt(rt2x00dev, RT3090)) {
2229 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2231 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2233 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2235 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
2237 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2238 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
2239 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2245 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2246 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2247 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®);
2249 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2255 if (rt2x00_rt(rt2x00dev, RT3070)) {
2256 rt2x00dev->calibration[0] =
2257 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2258 rt2x00dev->calibration[1] =
2259 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
2260 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2261 rt2x00_rt(rt2x00dev, RT3090) ||
2262 rt2x00_rt(rt2x00dev, RT3390)) {
2263 rt2x00dev->calibration[0] =
2264 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2265 rt2x00dev->calibration[1] =
2266 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
2272 rt2800_bbp_write(rt2x00dev, 24, 0);
2274 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2276 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2281 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2283 rt2800_bbp_write(rt2x00dev, 4, bbp);
2285 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2286 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2287 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2288 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
2289 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2291 rt2800_register_read(rt2x00dev, OPT_14_CSR, ®);
2293 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2295 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2297 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2298 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2299 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2300 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
2303 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2308 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2310 if (rt2x00_rt(rt2x00dev, RT3090)) {
2311 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2313 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2319 rt2800_bbp_write(rt2x00dev, 138, bbp);
2322 if (rt2x00_rt(rt2x00dev, RT3071) ||
2323 rt2x00_rt(rt2x00dev, RT3090) ||
2324 rt2x00_rt(rt2x00dev, RT3390)) {
2325 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2331 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2333 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2335 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2337 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2339 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2341 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2343 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2346 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
2347 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
2348 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2349 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
2356 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2363 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2367 rt2800_register_read(rt2x00dev, EFUSE_CTRL, ®);
2373 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2377 mutex_lock(&rt2x00dev->csr_mutex);
2379 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, ®);
2383 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
2386 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, ®);
2389 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2390 (u32 *)&rt2x00dev->eeprom[i]);
2391 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2392 (u32 *)&rt2x00dev->eeprom[i + 2]);
2393 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2394 (u32 *)&rt2x00dev->eeprom[i + 4]);
2395 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2396 (u32 *)&rt2x00dev->eeprom[i + 6]);
2398 mutex_unlock(&rt2x00dev->csr_mutex);
2401 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2406 rt2800_efuse_read(rt2x00dev, i);
2410 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2419 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2422 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2425 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2430 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2431 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2432 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
2433 rt2x00_rt(rt2x00dev, RT2872)) {
2439 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2442 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2456 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2457 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2460 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2463 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2464 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2470 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2471 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2472 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2473 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2474 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
2482 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2485 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2490 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2492 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2499 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2501 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2506 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2508 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2515 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2517 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
2522 rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
2528 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2537 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2543 rt2800_register_read(rt2x00dev, MAC_CSR0, ®);
2545 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2548 if (!rt2x00_rt(rt2x00dev, RT2860) &&
2549 !rt2x00_rt(rt2x00dev, RT2872) &&
2550 !rt2x00_rt(rt2x00dev, RT2883) &&
2551 !rt2x00_rt(rt2x00dev, RT3070) &&
2552 !rt2x00_rt(rt2x00dev, RT3071) &&
2553 !rt2x00_rt(rt2x00dev, RT3090) &&
2554 !rt2x00_rt(rt2x00dev, RT3390) &&
2555 !rt2x00_rt(rt2x00dev, RT3572)) {
2556 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2560 if (!rt2x00_rf(rt2x00dev, RF2820) &&
2561 !rt2x00_rf(rt2x00dev, RF2850) &&
2562 !rt2x00_rf(rt2x00dev, RF2720) &&
2563 !rt2x00_rf(rt2x00dev, RF2750) &&
2564 !rt2x00_rf(rt2x00dev, RF3020) &&
2565 !rt2x00_rf(rt2x00dev, RF2020) &&
2566 !rt2x00_rf(rt2x00dev, RF3021) &&
2567 !rt2x00_rf(rt2x00dev, RF3022) &&
2568 !rt2x00_rf(rt2x00dev, RF3052)) {
2569 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2576 rt2x00dev->default_ant.tx =
2578 rt2x00dev->default_ant.rx =
2584 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2585 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2590 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2593 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2595 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2601 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2607 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2608 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2609 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2611 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2759 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2761 struct hw_mode_spec *spec = &rt2x00dev->spec;
2772 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
2773 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2778 rt2x00dev->hw->flags =
2785 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2786 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2787 rt2x00_eeprom_addr(rt2x00dev,
2799 rt2x00dev->hw->max_rates = 7;
2800 rt2x00dev->hw->max_rate_tries = 1;
2802 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2810 if (rt2x00_rf(rt2x00dev, RF2820) ||
2811 rt2x00_rf(rt2x00dev, RF2720)) {
2814 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
2815 rt2x00_rf(rt2x00dev, RF2750)) {
2819 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2820 rt2x00_rf(rt2x00dev, RF2020) ||
2821 rt2x00_rf(rt2x00dev, RF3021) ||
2822 rt2x00_rf(rt2x00dev, RF3022)) {
2825 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
2834 if (!rt2x00_rf(rt2x00dev, RF2020))
2880 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
2882 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2883 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2893 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2894 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2913 struct rt2x00_dev *rt2x00dev = hw->priv;
2918 rt2800_register_multiread(rt2x00dev, offset,
2928 struct rt2x00_dev *rt2x00dev = hw->priv;
2932 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®);
2934 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2936 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®);
2938 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2940 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
2942 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2944 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®);
2946 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2948 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®);
2950 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2952 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®);
2954 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2956 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®);
2958 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2967 struct rt2x00_dev *rt2x00dev = hw->priv;
2991 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2998 rt2800_register_read(rt2x00dev, offset, ®);
3000 rt2800_register_write(rt2x00dev, offset, reg);
3006 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®);
3008 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3010 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®);
3012 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3014 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®);
3016 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3021 rt2800_register_read(rt2x00dev, offset, ®);
3026 rt2800_register_write(rt2x00dev, offset, reg);
3034 struct rt2x00_dev *rt2x00dev = hw->priv;
3038 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®);
3040 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®);