Lines Matching refs:FIELD32
107 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
108 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
109 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
110 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
111 #define E2PROM_CSR_TYPE FIELD32(0x00000030)
112 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
113 #define E2PROM_CSR_RELOAD FIELD32(0x00000080)
119 #define OPT_14_CSR_BIT0 FIELD32(0x00000001)
127 #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
128 #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
129 #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
130 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
131 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
132 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
133 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
134 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
135 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
136 #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
137 #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
138 #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
139 #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
140 #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
141 #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
142 #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
143 #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
144 #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
150 #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
151 #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
152 #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
153 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
154 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
155 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
156 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
157 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
158 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
159 #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
160 #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
161 #define INT_MASK_CSR_TBTT FIELD32(0x00000800)
162 #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
163 #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
164 #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
165 #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
166 #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
167 #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
173 #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
174 #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
175 #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
176 #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
177 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
178 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
179 #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
180 #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
181 #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
187 #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
188 #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
189 #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
190 #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
191 #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
192 #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
193 #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
199 #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
200 #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
201 #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
202 #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
203 #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
204 #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
214 #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
215 #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
216 #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
217 #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
227 #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
228 #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
229 #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
230 #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
240 #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
241 #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
242 #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
243 #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
251 #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
252 #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
260 #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
261 #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
267 #define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
268 #define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
269 #define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
270 #define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
271 #define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
272 #define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
273 #define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
274 #define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
275 #define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
353 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
354 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
355 #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
356 #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
357 #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
358 #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
359 #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
360 #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
361 #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
362 #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
363 #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
369 #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
376 #define PBF_SYS_CTRL_READY FIELD32(0x00000080)
377 #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
383 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
399 #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
400 #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
401 #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
402 #define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
408 #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
409 #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
410 #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
411 #define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
424 #define RF_CSR_CFG_DATA FIELD32(0x000000ff)
425 #define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
426 #define RF_CSR_CFG_WRITE FIELD32(0x00010000)
427 #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
433 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
434 #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
435 #define EFUSE_CTRL_KICK FIELD32(0x40000000)
436 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
462 #define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
463 #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
464 #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
465 #define LDO_CFG0_BGSEL FIELD32(0x03000000)
466 #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
467 #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
468 #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
474 #define GPIO_SWITCH_0 FIELD32(0x00000001)
475 #define GPIO_SWITCH_1 FIELD32(0x00000002)
476 #define GPIO_SWITCH_2 FIELD32(0x00000004)
477 #define GPIO_SWITCH_3 FIELD32(0x00000008)
478 #define GPIO_SWITCH_4 FIELD32(0x00000010)
479 #define GPIO_SWITCH_5 FIELD32(0x00000020)
480 #define GPIO_SWITCH_6 FIELD32(0x00000040)
481 #define GPIO_SWITCH_7 FIELD32(0x00000080)
494 #define MAC_CSR0_REVISION FIELD32(0x0000ffff)
495 #define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
501 #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
502 #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
503 #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
504 #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
505 #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
506 #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
507 #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
508 #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
514 #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
515 #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
516 #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
517 #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
528 #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
529 #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
530 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
536 #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
537 #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
538 #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
539 #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
553 #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
554 #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
555 #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
556 #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
565 #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
566 #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
567 #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
568 #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
580 #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
581 #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
582 #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
583 #define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
584 #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
585 #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
596 #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
597 #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
598 #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
599 #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
600 #define RF_CSR_CFG0_SEL FIELD32(0x40000000)
601 #define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
611 #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
612 #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
619 #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
633 #define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
634 #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
635 #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
636 #define LED_CFG_R_LED_MODE FIELD32(0x03000000)
637 #define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
638 #define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
639 #define LED_CFG_LED_POLAR FIELD32(0x40000000)
652 #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
653 #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
654 #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
655 #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
656 #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
662 #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
663 #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
669 #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
670 #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
671 #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
672 #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
692 #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
693 #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
694 #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
695 #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
696 #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
697 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
708 #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
714 #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
727 #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
728 #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
734 #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
735 #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
753 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
766 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
767 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
768 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
774 #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
775 #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
776 #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
777 #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
783 #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
784 #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
785 #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
786 #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
792 #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
793 #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
794 #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
795 #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
801 #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
802 #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
803 #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
804 #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
814 #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
815 #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
816 #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
817 #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
818 #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
819 #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
820 #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
821 #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
827 #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
828 #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
829 #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
830 #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
831 #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
832 #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
833 #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
834 #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
840 #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
841 #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
842 #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
843 #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
844 #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
845 #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
846 #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
847 #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
853 #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
854 #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
855 #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
856 #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
857 #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
858 #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
859 #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
860 #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
866 #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
867 #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
868 #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
869 #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
870 #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
871 #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
872 #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
873 #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
879 #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
880 #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
881 #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
882 #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
888 #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
889 #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
890 #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
891 #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
892 #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
893 #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
894 #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
895 #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
896 #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
897 #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
898 #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
899 #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
900 #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
901 #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
902 #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
903 #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
904 #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
905 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
906 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
907 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
913 #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
914 #define TX_BAND_CFG_A FIELD32(0x00000002)
915 #define TX_BAND_CFG_BG FIELD32(0x00000004)
948 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
949 #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
950 #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
961 #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
962 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
963 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
977 #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
978 #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
979 #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
980 #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
981 #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
982 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
997 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
998 #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
999 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
1000 #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
1001 #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
1002 #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
1003 #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
1004 #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
1010 #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
1011 #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
1012 #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
1013 #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
1014 #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
1015 #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
1016 #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
1017 #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
1023 #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
1024 #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
1025 #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
1026 #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
1027 #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
1028 #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
1029 #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
1030 #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
1036 #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
1037 #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
1038 #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
1039 #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
1040 #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
1041 #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
1042 #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
1043 #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
1049 #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
1050 #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
1051 #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
1052 #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
1070 #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1071 #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1072 #define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1073 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1074 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1075 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1076 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1077 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1078 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1079 #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1085 #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1086 #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1087 #define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1088 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1089 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1090 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1091 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1092 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1093 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1094 #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1100 #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1101 #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1102 #define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1103 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1104 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1105 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1106 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1107 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1108 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1109 #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1115 #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1116 #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1117 #define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1118 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1119 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1120 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1121 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1122 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1123 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1124 #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1130 #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1131 #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1132 #define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1133 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1134 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1135 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1136 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1137 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1138 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1139 #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1145 #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1146 #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1147 #define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1148 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1149 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1150 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1151 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1152 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1153 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1154 #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1170 #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1171 #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1172 #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1173 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1174 #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1175 #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1176 #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1177 #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1178 #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1179 #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1180 #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1181 #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1182 #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1183 #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1184 #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1185 #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1186 #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1199 #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1200 #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1201 #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1202 #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1203 #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1204 #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1205 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1282 #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1283 #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1289 #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1290 #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1296 #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1297 #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1303 #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1304 #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1310 #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1311 #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1317 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1318 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1324 #define TX_STA_FIFO_VALID FIELD32(0x00000001)
1325 #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1326 #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1327 #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1328 #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1329 #define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1330 #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1331 #define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1332 #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1338 #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1339 #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1345 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1346 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1352 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1353 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1359 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1360 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1366 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1367 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1373 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1374 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1380 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1381 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1387 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1388 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1394 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1395 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1403 #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1404 #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1453 #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1454 #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1455 #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1456 #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1457 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
1458 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
1459 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
1460 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
1465 #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1466 #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1467 #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1468 #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1469 #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1470 #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1471 #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1472 #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1482 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1483 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1484 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1485 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1491 #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1492 #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1493 #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1494 #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1696 #define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1697 #define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1698 #define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1703 #define RF3_TXPOWER_G FIELD32(0x00003e00)
1704 #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1705 #define RF3_TXPOWER_A FIELD32(0x00003c00)
1710 #define RF4_TXPOWER_G FIELD32(0x000007c0)
1711 #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1712 #define RF4_TXPOWER_A FIELD32(0x00000780)
1713 #define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1714 #define RF4_HT40 FIELD32(0x00200000)
1939 #define TXWI_W0_FRAG FIELD32(0x00000001)
1940 #define TXWI_W0_MIMO_PS FIELD32(0x00000002)
1941 #define TXWI_W0_CF_ACK FIELD32(0x00000004)
1942 #define TXWI_W0_TS FIELD32(0x00000008)
1943 #define TXWI_W0_AMPDU FIELD32(0x00000010)
1944 #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
1945 #define TXWI_W0_TX_OP FIELD32(0x00000300)
1946 #define TXWI_W0_MCS FIELD32(0x007f0000)
1947 #define TXWI_W0_BW FIELD32(0x00800000)
1948 #define TXWI_W0_SHORT_GI FIELD32(0x01000000)
1949 #define TXWI_W0_STBC FIELD32(0x06000000)
1950 #define TXWI_W0_IFS FIELD32(0x08000000)
1951 #define TXWI_W0_PHYMODE FIELD32(0xc0000000)
1956 #define TXWI_W1_ACK FIELD32(0x00000001)
1957 #define TXWI_W1_NSEQ FIELD32(0x00000002)
1958 #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
1959 #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
1960 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1961 #define TXWI_W1_PACKETID FIELD32(0xf0000000)
1966 #define TXWI_W2_IV FIELD32(0xffffffff)
1971 #define TXWI_W3_EIV FIELD32(0xffffffff)
1980 #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
1981 #define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
1982 #define RXWI_W0_BSSID FIELD32(0x00001c00)
1983 #define RXWI_W0_UDF FIELD32(0x0000e000)
1984 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1985 #define RXWI_W0_TID FIELD32(0xf0000000)
1990 #define RXWI_W1_FRAG FIELD32(0x0000000f)
1991 #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
1992 #define RXWI_W1_MCS FIELD32(0x007f0000)
1993 #define RXWI_W1_BW FIELD32(0x00800000)
1994 #define RXWI_W1_SHORT_GI FIELD32(0x01000000)
1995 #define RXWI_W1_STBC FIELD32(0x06000000)
1996 #define RXWI_W1_PHYMODE FIELD32(0xc0000000)
2001 #define RXWI_W2_RSSI0 FIELD32(0x000000ff)
2002 #define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
2003 #define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
2008 #define RXWI_W3_SNR0 FIELD32(0x000000ff)
2009 #define RXWI_W3_SNR1 FIELD32(0x0000ff00)