Lines Matching refs:FIELD32
79 #define CSR0_REVISION FIELD32(0x0000ffff)
88 #define CSR1_SOFT_RESET FIELD32(0x00000001)
89 #define CSR1_BBP_RESET FIELD32(0x00000002)
90 #define CSR1_HOST_READY FIELD32(0x00000004)
101 #define CSR3_BYTE0 FIELD32(0x000000ff)
102 #define CSR3_BYTE1 FIELD32(0x0000ff00)
103 #define CSR3_BYTE2 FIELD32(0x00ff0000)
104 #define CSR3_BYTE3 FIELD32(0xff000000)
110 #define CSR4_BYTE4 FIELD32(0x000000ff)
111 #define CSR4_BYTE5 FIELD32(0x0000ff00)
117 #define CSR5_BYTE0 FIELD32(0x000000ff)
118 #define CSR5_BYTE1 FIELD32(0x0000ff00)
119 #define CSR5_BYTE2 FIELD32(0x00ff0000)
120 #define CSR5_BYTE3 FIELD32(0xff000000)
126 #define CSR6_BYTE4 FIELD32(0x000000ff)
127 #define CSR6_BYTE5 FIELD32(0x0000ff00)
155 #define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
156 #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
157 #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
158 #define CSR7_TXDONE_TXRING FIELD32(0x00000008)
159 #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
160 #define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
161 #define CSR7_RXDONE FIELD32(0x00000040)
162 #define CSR7_DECRYPTION_DONE FIELD32(0x00000080)
163 #define CSR7_ENCRYPTION_DONE FIELD32(0x00000100)
164 #define CSR7_UART1_TX_TRESHOLD FIELD32(0x00000200)
165 #define CSR7_UART1_RX_TRESHOLD FIELD32(0x00000400)
166 #define CSR7_UART1_IDLE_TRESHOLD FIELD32(0x00000800)
167 #define CSR7_UART1_TX_BUFF_ERROR FIELD32(0x00001000)
168 #define CSR7_UART1_RX_BUFF_ERROR FIELD32(0x00002000)
169 #define CSR7_UART2_TX_TRESHOLD FIELD32(0x00004000)
170 #define CSR7_UART2_RX_TRESHOLD FIELD32(0x00008000)
171 #define CSR7_UART2_IDLE_TRESHOLD FIELD32(0x00010000)
172 #define CSR7_UART2_TX_BUFF_ERROR FIELD32(0x00020000)
173 #define CSR7_UART2_RX_BUFF_ERROR FIELD32(0x00040000)
174 #define CSR7_TIMER_CSR3_EXPIRE FIELD32(0x00080000)
201 #define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
202 #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
203 #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
204 #define CSR8_TXDONE_TXRING FIELD32(0x00000008)
205 #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
206 #define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
207 #define CSR8_RXDONE FIELD32(0x00000040)
208 #define CSR8_DECRYPTION_DONE FIELD32(0x00000080)
209 #define CSR8_ENCRYPTION_DONE FIELD32(0x00000100)
210 #define CSR8_UART1_TX_TRESHOLD FIELD32(0x00000200)
211 #define CSR8_UART1_RX_TRESHOLD FIELD32(0x00000400)
212 #define CSR8_UART1_IDLE_TRESHOLD FIELD32(0x00000800)
213 #define CSR8_UART1_TX_BUFF_ERROR FIELD32(0x00001000)
214 #define CSR8_UART1_RX_BUFF_ERROR FIELD32(0x00002000)
215 #define CSR8_UART2_TX_TRESHOLD FIELD32(0x00004000)
216 #define CSR8_UART2_RX_TRESHOLD FIELD32(0x00008000)
217 #define CSR8_UART2_IDLE_TRESHOLD FIELD32(0x00010000)
218 #define CSR8_UART2_TX_BUFF_ERROR FIELD32(0x00020000)
219 #define CSR8_UART2_RX_BUFF_ERROR FIELD32(0x00040000)
220 #define CSR8_TIMER_CSR3_EXPIRE FIELD32(0x00080000)
227 #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
236 #define SECCSR0_KICK_DECRYPT FIELD32(0x00000001)
237 #define SECCSR0_ONE_SHOT FIELD32(0x00000002)
238 #define SECCSR0_DESC_ADDRESS FIELD32(0xfffffffc)
250 #define CSR11_CWMIN FIELD32(0x0000000f)
251 #define CSR11_CWMAX FIELD32(0x000000f0)
252 #define CSR11_SLOT_TIME FIELD32(0x00001f00)
253 #define CSR11_CW_SELECT FIELD32(0x00002000)
254 #define CSR11_LONG_RETRY FIELD32(0x00ff0000)
255 #define CSR11_SHORT_RETRY FIELD32(0xff000000)
264 #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
265 #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
274 #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
275 #define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
289 #define CSR14_TSF_COUNT FIELD32(0x00000001)
290 #define CSR14_TSF_SYNC FIELD32(0x00000006)
291 #define CSR14_TBCN FIELD32(0x00000008)
292 #define CSR14_TCFP FIELD32(0x00000010)
293 #define CSR14_TATIMW FIELD32(0x00000020)
294 #define CSR14_BEACON_GEN FIELD32(0x00000040)
295 #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
296 #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
305 #define CSR15_CFP FIELD32(0x00000001)
306 #define CSR15_ATIMW FIELD32(0x00000002)
307 #define CSR15_BEACON_SENT FIELD32(0x00000004)
313 #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
319 #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
327 #define CSR18_SIFS FIELD32(0x000001ff)
328 #define CSR18_PIFS FIELD32(0x001f0000)
336 #define CSR19_DIFS FIELD32(0x0000ffff)
337 #define CSR19_EIFS FIELD32(0xffff0000)
346 #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
347 #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
348 #define CSR20_AUTOWAKE FIELD32(0x01000000)
356 #define CSR21_RELOAD FIELD32(0x00000001)
357 #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
358 #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
359 #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
360 #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
361 #define CSR21_TYPE_93C46 FIELD32(0x00000020)
369 #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
370 #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
385 #define TXCSR0_KICK_TX FIELD32(0x00000001)
386 #define TXCSR0_KICK_ATIM FIELD32(0x00000002)
387 #define TXCSR0_KICK_PRIO FIELD32(0x00000004)
388 #define TXCSR0_ABORT FIELD32(0x00000008)
398 #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
399 #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
400 #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
401 #define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
411 #define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
412 #define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
413 #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
414 #define TXCSR2_NUM_PRIO FIELD32(0xff000000)
420 #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
426 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
432 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
438 #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
445 #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
451 #define TXCSR8_BBP_ID0 FIELD32(0x0000007f)
452 #define TXCSR8_BBP_ID0_VALID FIELD32(0x00000080)
453 #define TXCSR8_BBP_ID1 FIELD32(0x00007f00)
454 #define TXCSR8_BBP_ID1_VALID FIELD32(0x00008000)
455 #define TXCSR8_BBP_ID2 FIELD32(0x007f0000)
456 #define TXCSR8_BBP_ID2_VALID FIELD32(0x00800000)
457 #define TXCSR8_BBP_ID3 FIELD32(0x7f000000)
458 #define TXCSR8_BBP_ID3_VALID FIELD32(0x80000000)
468 #define TXCSR9_OFDM_RATE FIELD32(0x000000ff)
469 #define TXCSR9_OFDM_SERVICE FIELD32(0x0000ff00)
470 #define TXCSR9_OFDM_LENGTH_LOW FIELD32(0x00ff0000)
471 #define TXCSR9_OFDM_LENGTH_HIGH FIELD32(0xff000000)
495 #define RXCSR0_DISABLE_RX FIELD32(0x00000001)
496 #define RXCSR0_DROP_CRC FIELD32(0x00000002)
497 #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
498 #define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
499 #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
500 #define RXCSR0_DROP_TODS FIELD32(0x00000020)
501 #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
502 #define RXCSR0_PASS_CRC FIELD32(0x00000080)
503 #define RXCSR0_PASS_PLCP FIELD32(0x00000100)
504 #define RXCSR0_DROP_MCAST FIELD32(0x00000200)
505 #define RXCSR0_DROP_BCAST FIELD32(0x00000400)
506 #define RXCSR0_ENABLE_QOS FIELD32(0x00000800)
514 #define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
515 #define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
521 #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
529 #define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
530 #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
531 #define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
532 #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
533 #define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
534 #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
535 #define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
536 #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
544 #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
545 #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
546 #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
547 #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
568 #define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
569 #define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
570 #define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
571 #define PCICSR_BURST_LENTH FIELD32(0x00000060)
572 #define PCICSR_ENABLE_CLK FIELD32(0x00000080)
573 #define PCICSR_READ_MULTIPLE FIELD32(0x00000100)
574 #define PCICSR_WRITE_INVALID FIELD32(0x00000200)
581 #define CNT0_FCS_ERROR FIELD32(0x0000ffff)
597 #define CNT3_FALSE_CCA FIELD32(0x0000ffff)
635 #define PWRCSR1_SET_STATE FIELD32(0x00000001)
636 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
637 #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
638 #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
639 #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
640 #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
649 #define TIMECSR_US_COUNT FIELD32(0x000000ff)
650 #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
651 #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
669 #define MACCSR1_KICK_RX FIELD32(0x00000001)
670 #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
671 #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
672 #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
673 #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
674 #define MACCSR1_LOOPBACK FIELD32(0x00000060)
675 #define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
683 #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
684 #define RALINKCSR_AR_BBP_ID0 FIELD32(0x00007f00)
685 #define RALINKCSR_AR_BBP_VALID0 FIELD32(0x00008000)
686 #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
687 #define RALINKCSR_AR_BBP_ID1 FIELD32(0x7f000000)
688 #define RALINKCSR_AR_BBP_VALID1 FIELD32(0x80000000)
699 #define BCNCSR_CHANGE FIELD32(0x00000001)
700 #define BCNCSR_DELTATIME FIELD32(0x0000001e)
701 #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
702 #define BCNCSR_MODE FIELD32(0x00006000)
703 #define BCNCSR_PLUS FIELD32(0x00008000)
717 #define BBPCSR_VALUE FIELD32(0x000000ff)
718 #define BBPCSR_REGNUM FIELD32(0x00007f00)
719 #define BBPCSR_BUSY FIELD32(0x00008000)
720 #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
731 #define RFCSR_VALUE FIELD32(0x00ffffff)
732 #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
733 #define RFCSR_IF_SELECT FIELD32(0x20000000)
734 #define RFCSR_PLL_LD FIELD32(0x40000000)
735 #define RFCSR_BUSY FIELD32(0x80000000)
748 #define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
749 #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
750 #define LEDCSR_LINK FIELD32(0x00010000)
751 #define LEDCSR_ACTIVITY FIELD32(0x00020000)
752 #define LEDCSR_LINK_POLARITY FIELD32(0x00040000)
753 #define LEDCSR_ACTIVITY_POLARITY FIELD32(0x00080000)
754 #define LEDCSR_LED_DEFAULT FIELD32(0x00100000)
794 #define GPIOCSR_BIT0 FIELD32(0x00000001)
795 #define GPIOCSR_BIT1 FIELD32(0x00000002)
796 #define GPIOCSR_BIT2 FIELD32(0x00000004)
797 #define GPIOCSR_BIT3 FIELD32(0x00000008)
798 #define GPIOCSR_BIT4 FIELD32(0x00000010)
799 #define GPIOCSR_BIT5 FIELD32(0x00000020)
800 #define GPIOCSR_BIT6 FIELD32(0x00000040)
801 #define GPIOCSR_BIT7 FIELD32(0x00000080)
802 #define GPIOCSR_DIR0 FIELD32(0x00000100)
803 #define GPIOCSR_DIR1 FIELD32(0x00000200)
804 #define GPIOCSR_DIR2 FIELD32(0x00000400)
805 #define GPIOCSR_DIR3 FIELD32(0x00000800)
806 #define GPIOCSR_DIR4 FIELD32(0x00001000)
807 #define GPIOCSR_DIR5 FIELD32(0x00002000)
808 #define GPIOCSR_DIR6 FIELD32(0x00004000)
809 #define GPIOCSR_DIR7 FIELD32(0x00008000)
825 #define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
826 #define BCNCSR1_BEACON_CWMIN FIELD32(0x000f0000)
833 #define MACCSR2_DELAY FIELD32(0x000000ff)
844 #define ARCSR2_SIGNAL FIELD32(0x000000ff)
845 #define ARCSR2_SERVICE FIELD32(0x0000ff00)
846 #define ARCSR2_LENGTH FIELD32(0xffff0000)
852 #define ARCSR3_SIGNAL FIELD32(0x000000ff)
853 #define ARCSR3_SERVICE FIELD32(0x0000ff00)
854 #define ARCSR3_LENGTH FIELD32(0xffff0000)
860 #define ARCSR4_SIGNAL FIELD32(0x000000ff)
861 #define ARCSR4_SERVICE FIELD32(0x0000ff00)
862 #define ARCSR4_LENGTH FIELD32(0xffff0000)
868 #define ARCSR5_SIGNAL FIELD32(0x000000ff)
869 #define ARCSR5_SERVICE FIELD32(0x0000ff00)
870 #define ARCSR5_LENGTH FIELD32(0xffff0000)
876 #define ARTCSR0_ACK_CTS_11MBS FIELD32(0x000000ff)
877 #define ARTCSR0_ACK_CTS_5_5MBS FIELD32(0x0000ff00)
878 #define ARTCSR0_ACK_CTS_2MBS FIELD32(0x00ff0000)
879 #define ARTCSR0_ACK_CTS_1MBS FIELD32(0xff000000)
886 #define ARTCSR1_ACK_CTS_6MBS FIELD32(0x000000ff)
887 #define ARTCSR1_ACK_CTS_9MBS FIELD32(0x0000ff00)
888 #define ARTCSR1_ACK_CTS_12MBS FIELD32(0x00ff0000)
889 #define ARTCSR1_ACK_CTS_18MBS FIELD32(0xff000000)
895 #define ARTCSR2_ACK_CTS_24MBS FIELD32(0x000000ff)
896 #define ARTCSR2_ACK_CTS_36MBS FIELD32(0x0000ff00)
897 #define ARTCSR2_ACK_CTS_48MBS FIELD32(0x00ff0000)
898 #define ARTCSR2_ACK_CTS_54MBS FIELD32(0xff000000)
907 #define SECCSR1_KICK_ENCRYPT FIELD32(0x00000001)
908 #define SECCSR1_ONE_SHOT FIELD32(0x00000002)
909 #define SECCSR1_DESC_ADDRESS FIELD32(0xfffffffc)
915 #define BBPCSR1_CCK FIELD32(0x00000003)
916 #define BBPCSR1_CCK_FLIP FIELD32(0x00000004)
917 #define BBPCSR1_OFDM FIELD32(0x00030000)
918 #define BBPCSR1_OFDM_FLIP FIELD32(0x00040000)
1003 #define RF1_TUNER FIELD32(0x00020000)
1008 #define RF3_TUNER FIELD32(0x00000100)
1009 #define RF3_TXPOWER FIELD32(0x00003e00)
1101 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
1102 #define TXD_W0_VALID FIELD32(0x00000002)
1103 #define TXD_W0_RESULT FIELD32(0x0000001c)
1104 #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
1105 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
1106 #define TXD_W0_ACK FIELD32(0x00000200)
1107 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
1108 #define TXD_W0_OFDM FIELD32(0x00000800)
1109 #define TXD_W0_CIPHER_OWNER FIELD32(0x00001000)
1110 #define TXD_W0_IFS FIELD32(0x00006000)
1111 #define TXD_W0_RETRY_MODE FIELD32(0x00008000)
1112 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1113 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1118 #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
1123 #define TXD_W2_IV_OFFSET FIELD32(0x0000003f)
1124 #define TXD_W2_AIFS FIELD32(0x000000c0)
1125 #define TXD_W2_CWMIN FIELD32(0x00000f00)
1126 #define TXD_W2_CWMAX FIELD32(0x0000f000)
1131 #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff)
1132 #define TXD_W3_PLCP_SERVICE FIELD32(0x0000ff00)
1133 #define TXD_W3_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
1134 #define TXD_W3_PLCP_LENGTH_HIGH FIELD32(0xff000000)
1139 #define TXD_W4_IV FIELD32(0xffffffff)
1144 #define TXD_W5_EIV FIELD32(0xffffffff)
1149 #define TXD_W6_KEY FIELD32(0xffffffff)
1150 #define TXD_W7_KEY FIELD32(0xffffffff)
1151 #define TXD_W8_KEY FIELD32(0xffffffff)
1152 #define TXD_W9_KEY FIELD32(0xffffffff)
1157 #define TXD_W10_RTS FIELD32(0x00000001)
1158 #define TXD_W10_TX_RATE FIELD32(0x000000fe)
1167 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1168 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
1169 #define RXD_W0_MULTICAST FIELD32(0x00000004)
1170 #define RXD_W0_BROADCAST FIELD32(0x00000008)
1171 #define RXD_W0_MY_BSS FIELD32(0x00000010)
1172 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
1173 #define RXD_W0_OFDM FIELD32(0x00000040)
1174 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
1175 #define RXD_W0_CIPHER_OWNER FIELD32(0x00000100)
1176 #define RXD_W0_ICV_ERROR FIELD32(0x00000200)
1177 #define RXD_W0_IV_OFFSET FIELD32(0x0000fc00)
1178 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1179 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1184 #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
1189 #define RXD_W2_SIGNAL FIELD32(0x000000ff)
1190 #define RXD_W2_RSSI FIELD32(0x0000ff00)
1191 #define RXD_W2_TA FIELD32(0xffff0000)
1196 #define RXD_W3_TA FIELD32(0xffffffff)
1201 #define RXD_W4_IV FIELD32(0xffffffff)
1206 #define RXD_W5_EIV FIELD32(0xffffffff)
1211 #define RXD_W6_KEY FIELD32(0xffffffff)
1212 #define RXD_W7_KEY FIELD32(0xffffffff)
1213 #define RXD_W8_KEY FIELD32(0xffffffff)
1214 #define RXD_W9_KEY FIELD32(0xffffffff)
1219 #define RXD_W10_DROP FIELD32(0x00000001)