Lines Matching refs:word
59 const unsigned int word, const u8 value)
72 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
83 const unsigned int word, u8 *value)
99 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
114 const unsigned int word, const u32 value)
132 rt2x00_rf_write(rt2x00dev, word, value);
716 u32 word;
719 rt2x00_desc_read(entry_priv->desc, 0, &word);
721 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
723 rt2x00_desc_read(entry_priv->desc, 0, &word);
725 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
726 rt2x00_get_field32(word, TXD_W0_VALID));
734 u32 word;
737 rt2x00_desc_read(entry_priv->desc, 1, &word);
738 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
739 rt2x00_desc_write(entry_priv->desc, 1, word);
741 rt2x00_desc_read(entry_priv->desc, 0, &word);
742 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
743 rt2x00_desc_write(entry_priv->desc, 0, word);
745 rt2x00_desc_read(entry_priv->desc, 0, &word);
746 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
747 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
748 rt2x00_desc_write(entry_priv->desc, 0, word);
1171 u32 word;
1176 rt2x00_desc_read(txd, 1, &word);
1177 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1178 rt2x00_desc_write(txd, 1, word);
1180 rt2x00_desc_read(txd, 2, &word);
1181 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1182 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1183 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1184 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1185 rt2x00_desc_write(txd, 2, word);
1187 rt2x00_desc_read(txd, 3, &word);
1188 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1189 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1190 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1191 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1192 rt2x00_desc_write(txd, 3, word);
1194 rt2x00_desc_read(txd, 10, &word);
1195 rt2x00_set_field32(&word, TXD_W10_RTS,
1197 rt2x00_desc_write(txd, 10, word);
1200 * Writing TXD word 0 must the last to prevent a race condition with
1204 rt2x00_desc_read(txd, 0, &word);
1205 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1206 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1207 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1209 rt2x00_set_field32(&word, TXD_W0_ACK,
1211 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1213 rt2x00_set_field32(&word, TXD_W0_OFDM,
1215 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1216 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1217 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1219 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1220 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1221 rt2x00_desc_write(txd, 0, word);
1341 u32 word;
1346 rt2x00_desc_read(entry_priv->desc, 0, &word);
1348 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1349 !rt2x00_get_field32(word, TXD_W0_VALID))
1356 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1367 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1456 u16 word;
1483 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1484 if (word == 0xffff) {
1485 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1486 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1488 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1490 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1492 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1493 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1494 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1495 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1496 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1499 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1500 if (word == 0xffff) {
1501 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1502 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1503 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1504 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1505 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1508 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1509 if (word == 0xffff) {
1510 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1512 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1513 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1526 * Read EEPROM word for configuration.