Lines Matching refs:rt2x00dev
58 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
63 mutex_lock(&rt2x00dev->csr_mutex);
69 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
76 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
79 mutex_unlock(&rt2x00dev->csr_mutex);
82 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
87 mutex_lock(&rt2x00dev->csr_mutex);
97 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
103 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
105 WAIT_FOR_BBP(rt2x00dev, ®);
110 mutex_unlock(&rt2x00dev->csr_mutex);
113 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
118 mutex_lock(&rt2x00dev->csr_mutex);
124 if (WAIT_FOR_RF(rt2x00dev, ®)) {
131 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
132 rt2x00_rf_write(rt2x00dev, word, value);
135 mutex_unlock(&rt2x00dev->csr_mutex);
140 struct rt2x00_dev *rt2x00dev = eeprom->data;
143 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
155 struct rt2x00_dev *rt2x00dev = eeprom->data;
165 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
203 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
207 rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
220 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
227 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
238 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
241 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
246 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
250 led->rt2x00dev = rt2x00dev;
261 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
272 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
283 !rt2x00dev->intf_ap_count);
288 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
291 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
296 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
305 rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
308 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
313 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
317 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
321 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
325 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
329 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
340 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
345 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
347 rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
351 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
353 rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
357 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
359 rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
363 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
365 rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
369 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
371 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
373 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
375 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
377 rt2x00pci_register_read(rt2x00dev, CSR12, ®);
380 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
382 rt2x00pci_register_read(rt2x00dev, CSR18, ®);
385 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
387 rt2x00pci_register_read(rt2x00dev, CSR19, ®);
390 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
393 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
407 rt2x00pci_register_read(rt2x00dev, BBPCSR1, ®);
408 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
409 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
444 if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
452 if (rt2x00_rf(rt2x00dev, RF2525E))
459 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
460 rt2500pci_bbp_write(rt2x00dev, 14, r14);
461 rt2500pci_bbp_write(rt2x00dev, 2, r2);
464 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
478 if (!rt2x00_rf(rt2x00dev, RF2523))
485 if (rt2x00_rf(rt2x00dev, RF2525)) {
493 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
494 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
495 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
497 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
500 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
501 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
502 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
504 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
511 rt2500pci_bbp_write(rt2x00dev, 70, r70);
519 if (!rt2x00_rf(rt2x00dev, RF2523)) {
521 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
525 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
530 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
533 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
538 rt2x00_rf_read(rt2x00dev, 3, &rf3);
540 rt2500pci_rf_write(rt2x00dev, 3, rf3);
543 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
548 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
553 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
556 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
565 rt2x00pci_register_read(rt2x00dev, CSR20, ®);
567 (rt2x00dev->beacon_int - 20) * 16);
573 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
576 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
578 rt2x00pci_register_read(rt2x00dev, CSR20, ®);
580 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
583 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
586 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
591 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
595 rt2500pci_config_txpower(rt2x00dev,
598 rt2500pci_config_retry_limit(rt2x00dev, libconf);
600 rt2500pci_config_ps(rt2x00dev, libconf);
606 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
614 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
620 rt2x00pci_register_read(rt2x00dev, CNT3, ®);
624 static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
628 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
634 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
637 rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
640 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
648 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D &&
649 rt2x00dev->intf_associated && count > 20)
658 if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D ||
659 !rt2x00dev->intf_associated)
669 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
677 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
685 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
694 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
705 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
707 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
752 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
760 rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
761 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
762 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
763 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
764 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
765 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
767 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
768 rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
771 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
773 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
774 rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
777 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
779 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
780 rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
783 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
785 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
786 rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
789 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
791 rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
792 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
793 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
794 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
796 entry_priv = rt2x00dev->rx->entries[0].priv_data;
797 rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
800 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
805 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
809 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
810 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
811 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
812 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
814 rt2x00pci_register_read(rt2x00dev, TIMECSR, ®);
818 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
820 rt2x00pci_register_read(rt2x00dev, CSR9, ®);
822 rt2x00dev->rx->data_size / 128);
823 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
828 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
830 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
832 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
841 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
843 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
845 rt2x00pci_register_read(rt2x00dev, TXCSR8, ®);
854 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
856 rt2x00pci_register_read(rt2x00dev, ARTCSR0, ®);
861 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
863 rt2x00pci_register_read(rt2x00dev, ARTCSR1, ®);
868 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
870 rt2x00pci_register_read(rt2x00dev, ARTCSR2, ®);
875 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
877 rt2x00pci_register_read(rt2x00dev, RXCSR3, ®);
886 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
888 rt2x00pci_register_read(rt2x00dev, PCICSR, ®);
896 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
898 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
900 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
901 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
903 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
906 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
907 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
909 rt2x00pci_register_read(rt2x00dev, MACCSR2, ®);
911 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
913 rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®);
920 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
922 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
924 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
926 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
930 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
932 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
935 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
942 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
943 rt2x00pci_register_read(rt2x00dev, CNT4, ®);
948 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
954 rt2500pci_bbp_read(rt2x00dev, 0, &value);
960 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
964 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
971 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
974 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
975 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
976 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
977 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
978 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
979 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
980 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
981 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
982 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
983 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
984 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
985 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
986 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
987 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
988 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
989 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
990 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
991 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
992 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
993 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
994 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
995 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
996 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
997 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
998 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
999 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1000 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1001 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1002 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1003 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1006 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1011 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1021 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1026 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
1030 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1033 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1045 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
1046 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1053 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
1059 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1062 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1067 if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1068 rt2500pci_init_registers(rt2x00dev) ||
1069 rt2500pci_init_bbp(rt2x00dev)))
1075 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1080 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1083 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1094 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
1099 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1107 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®2);
1112 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1119 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1126 retval = rt2500pci_enable_radio(rt2x00dev);
1129 rt2500pci_disable_radio(rt2x00dev);
1135 rt2500pci_toggle_rx(rt2x00dev, state);
1141 rt2500pci_toggle_irq(rt2x00dev, state);
1147 retval = rt2500pci_set_state(rt2x00dev, state);
1155 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1164 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1236 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1243 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
1245 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1247 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1252 rt2500pci_write_tx_desc(rt2x00dev, entry->skb, txdesc);
1257 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1265 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1268 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1273 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
1277 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1280 static void rt2500pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1286 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1288 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
1290 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1320 entry->queue->rt2x00dev->rssi_offset;
1334 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1337 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1375 struct rt2x00_dev *rt2x00dev = dev_instance;
1376 u32 reg = rt2x00dev->irqvalue[0];
1388 rt2x00lib_beacondone(rt2x00dev);
1394 rt2x00pci_rxdone(rt2x00dev);
1400 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1406 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1412 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1415 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1423 struct rt2x00_dev *rt2x00dev = dev_instance;
1430 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
1431 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1436 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1440 rt2x00dev->irqvalue[0] = reg;
1443 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1452 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1459 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
1461 eeprom.data = rt2x00dev;
1471 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1477 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1480 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1483 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1495 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1496 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1499 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1504 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1505 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1508 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1512 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1513 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1519 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1528 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1534 rt2x00pci_register_read(rt2x00dev, CSR0, ®);
1535 rt2x00_set_chip(rt2x00dev, RT2560, value,
1538 if (!rt2x00_rf(rt2x00dev, RF2522) &&
1539 !rt2x00_rf(rt2x00dev, RF2523) &&
1540 !rt2x00_rf(rt2x00dev, RF2524) &&
1541 !rt2x00_rf(rt2x00dev, RF2525) &&
1542 !rt2x00_rf(rt2x00dev, RF2525E) &&
1543 !rt2x00_rf(rt2x00dev, RF5222)) {
1544 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1551 rt2x00dev->default_ant.tx =
1553 rt2x00dev->default_ant.rx =
1562 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1566 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1574 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1579 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1581 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
1586 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1587 rt2x00dev->rssi_offset =
1748 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1750 struct hw_mode_spec *spec = &rt2x00dev->spec;
1758 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1763 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1764 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1765 rt2x00_eeprom_addr(rt2x00dev,
1774 if (rt2x00_rf(rt2x00dev, RF2522)) {
1777 } else if (rt2x00_rf(rt2x00dev, RF2523)) {
1780 } else if (rt2x00_rf(rt2x00dev, RF2524)) {
1783 } else if (rt2x00_rf(rt2x00dev, RF2525)) {
1786 } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
1789 } else if (rt2x00_rf(rt2x00dev, RF5222)) {
1804 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1820 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1827 retval = rt2500pci_validate_eeprom(rt2x00dev);
1831 retval = rt2500pci_init_eeprom(rt2x00dev);
1838 retval = rt2500pci_probe_hw_mode(rt2x00dev);
1845 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1846 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1851 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1861 struct rt2x00_dev *rt2x00dev = hw->priv;
1865 rt2x00pci_register_read(rt2x00dev, CSR17, ®);
1867 rt2x00pci_register_read(rt2x00dev, CSR16, ®);
1875 struct rt2x00_dev *rt2x00dev = hw->priv;
1878 rt2x00pci_register_read(rt2x00dev, CSR15, ®);