Lines Matching refs:FIELD32
68 #define CSR0_REVISION FIELD32(0x0000ffff)
77 #define CSR1_SOFT_RESET FIELD32(0x00000001)
78 #define CSR1_BBP_RESET FIELD32(0x00000002)
79 #define CSR1_HOST_READY FIELD32(0x00000004)
90 #define CSR3_BYTE0 FIELD32(0x000000ff)
91 #define CSR3_BYTE1 FIELD32(0x0000ff00)
92 #define CSR3_BYTE2 FIELD32(0x00ff0000)
93 #define CSR3_BYTE3 FIELD32(0xff000000)
99 #define CSR4_BYTE4 FIELD32(0x000000ff)
100 #define CSR4_BYTE5 FIELD32(0x0000ff00)
106 #define CSR5_BYTE0 FIELD32(0x000000ff)
107 #define CSR5_BYTE1 FIELD32(0x0000ff00)
108 #define CSR5_BYTE2 FIELD32(0x00ff0000)
109 #define CSR5_BYTE3 FIELD32(0xff000000)
115 #define CSR6_BYTE4 FIELD32(0x000000ff)
116 #define CSR6_BYTE5 FIELD32(0x0000ff00)
130 #define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
131 #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
132 #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
133 #define CSR7_TXDONE_TXRING FIELD32(0x00000008)
134 #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
135 #define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
136 #define CSR7_RXDONE FIELD32(0x00000040)
150 #define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
151 #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
152 #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
153 #define CSR8_TXDONE_TXRING FIELD32(0x00000008)
154 #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
155 #define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
156 #define CSR8_RXDONE FIELD32(0x00000040)
163 #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
174 #define CSR11_CWMIN FIELD32(0x0000000f)
175 #define CSR11_CWMAX FIELD32(0x000000f0)
176 #define CSR11_SLOT_TIME FIELD32(0x00001f00)
177 #define CSR11_LONG_RETRY FIELD32(0x00ff0000)
178 #define CSR11_SHORT_RETRY FIELD32(0xff000000)
187 #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
188 #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
197 #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
198 #define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
212 #define CSR14_TSF_COUNT FIELD32(0x00000001)
213 #define CSR14_TSF_SYNC FIELD32(0x00000006)
214 #define CSR14_TBCN FIELD32(0x00000008)
215 #define CSR14_TCFP FIELD32(0x00000010)
216 #define CSR14_TATIMW FIELD32(0x00000020)
217 #define CSR14_BEACON_GEN FIELD32(0x00000040)
218 #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
219 #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
228 #define CSR15_CFP FIELD32(0x00000001)
229 #define CSR15_ATIMW FIELD32(0x00000002)
230 #define CSR15_BEACON_SENT FIELD32(0x00000004)
236 #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
242 #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
250 #define CSR18_SIFS FIELD32(0x0000ffff)
251 #define CSR18_PIFS FIELD32(0xffff0000)
259 #define CSR19_DIFS FIELD32(0x0000ffff)
260 #define CSR19_EIFS FIELD32(0xffff0000)
269 #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
270 #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
271 #define CSR20_AUTOWAKE FIELD32(0x01000000)
279 #define CSR21_RELOAD FIELD32(0x00000001)
280 #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
281 #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
282 #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
283 #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
284 #define CSR21_TYPE_93C46 FIELD32(0x00000020)
292 #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
293 #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
308 #define TXCSR0_KICK_TX FIELD32(0x00000001)
309 #define TXCSR0_KICK_ATIM FIELD32(0x00000002)
310 #define TXCSR0_KICK_PRIO FIELD32(0x00000004)
311 #define TXCSR0_ABORT FIELD32(0x00000008)
321 #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
322 #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
323 #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
324 #define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
334 #define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
335 #define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
336 #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
337 #define TXCSR2_NUM_PRIO FIELD32(0xff000000)
343 #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
349 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
355 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
361 #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
368 #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
387 #define RXCSR0_DISABLE_RX FIELD32(0x00000001)
388 #define RXCSR0_DROP_CRC FIELD32(0x00000002)
389 #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
390 #define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
391 #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
392 #define RXCSR0_DROP_TODS FIELD32(0x00000020)
393 #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
394 #define RXCSR0_PASS_CRC FIELD32(0x00000080)
402 #define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
403 #define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
409 #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
417 #define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
418 #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
419 #define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
420 #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
421 #define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
422 #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
423 #define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
424 #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
432 #define RXCSR4_BBP_ID4 FIELD32(0x0000007f)
433 #define RXCSR4_BBP_ID4_VALID FIELD32(0x00000080)
434 #define RXCSR4_BBP_ID5 FIELD32(0x00007f00)
435 #define RXCSR4_BBP_ID5_VALID FIELD32(0x00008000)
443 #define ARCSR0_AR_BBP_DATA0 FIELD32(0x000000ff)
444 #define ARCSR0_AR_BBP_ID0 FIELD32(0x0000ff00)
445 #define ARCSR0_AR_BBP_DATA1 FIELD32(0x00ff0000)
446 #define ARCSR0_AR_BBP_ID1 FIELD32(0xff000000)
454 #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
455 #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
456 #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
457 #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
475 #define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
476 #define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
477 #define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
478 #define PCICSR_BURST_LENTH FIELD32(0x00000060)
479 #define PCICSR_ENABLE_CLK FIELD32(0x00000080)
486 #define CNT0_FCS_ERROR FIELD32(0x0000ffff)
532 #define PWRCSR1_SET_STATE FIELD32(0x00000001)
533 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
534 #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
535 #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
536 #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
537 #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
546 #define TIMECSR_US_COUNT FIELD32(0x000000ff)
547 #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
548 #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
566 #define MACCSR1_KICK_RX FIELD32(0x00000001)
567 #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
568 #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
569 #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
570 #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
571 #define MACCSR1_LOOPBACK FIELD32(0x00000060)
572 #define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
580 #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
581 #define RALINKCSR_AR_BBP_ID0 FIELD32(0x0000ff00)
582 #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
583 #define RALINKCSR_AR_BBP_ID1 FIELD32(0xff000000)
594 #define BCNCSR_CHANGE FIELD32(0x00000001)
595 #define BCNCSR_DELTATIME FIELD32(0x0000001e)
596 #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
597 #define BCNCSR_MODE FIELD32(0x00006000)
598 #define BCNCSR_PLUS FIELD32(0x00008000)
612 #define BBPCSR_VALUE FIELD32(0x000000ff)
613 #define BBPCSR_REGNUM FIELD32(0x00007f00)
614 #define BBPCSR_BUSY FIELD32(0x00008000)
615 #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
626 #define RFCSR_VALUE FIELD32(0x00ffffff)
627 #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
628 #define RFCSR_IF_SELECT FIELD32(0x20000000)
629 #define RFCSR_PLL_LD FIELD32(0x40000000)
630 #define RFCSR_BUSY FIELD32(0x80000000)
640 #define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
641 #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
642 #define LEDCSR_LINK FIELD32(0x00010000)
643 #define LEDCSR_ACTIVITY FIELD32(0x00020000)
665 #define GPIOCSR_BIT0 FIELD32(0x00000001)
666 #define GPIOCSR_BIT1 FIELD32(0x00000002)
667 #define GPIOCSR_BIT2 FIELD32(0x00000004)
668 #define GPIOCSR_BIT3 FIELD32(0x00000008)
669 #define GPIOCSR_BIT4 FIELD32(0x00000010)
670 #define GPIOCSR_BIT5 FIELD32(0x00000020)
671 #define GPIOCSR_BIT6 FIELD32(0x00000040)
672 #define GPIOCSR_BIT7 FIELD32(0x00000080)
684 #define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
691 #define MACCSR2_DELAY FIELD32(0x000000ff)
697 #define ARCSR2_SIGNAL FIELD32(0x000000ff)
698 #define ARCSR2_SERVICE FIELD32(0x0000ff00)
699 #define ARCSR2_LENGTH_LOW FIELD32(0x00ff0000)
700 #define ARCSR2_LENGTH FIELD32(0xffff0000)
706 #define ARCSR3_SIGNAL FIELD32(0x000000ff)
707 #define ARCSR3_SERVICE FIELD32(0x0000ff00)
708 #define ARCSR3_LENGTH FIELD32(0xffff0000)
714 #define ARCSR4_SIGNAL FIELD32(0x000000ff)
715 #define ARCSR4_SERVICE FIELD32(0x0000ff00)
716 #define ARCSR4_LENGTH FIELD32(0xffff0000)
722 #define ARCSR5_SIGNAL FIELD32(0x000000ff)
723 #define ARCSR5_SERVICE FIELD32(0x0000ff00)
724 #define ARCSR5_LENGTH FIELD32(0xffff0000)
748 #define RF1_TUNER FIELD32(0x00020000)
753 #define RF3_TUNER FIELD32(0x00000100)
754 #define RF3_TXPOWER FIELD32(0x00003e00)
822 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
823 #define TXD_W0_VALID FIELD32(0x00000002)
824 #define TXD_W0_RESULT FIELD32(0x0000001c)
825 #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
826 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
827 #define TXD_W0_ACK FIELD32(0x00000200)
828 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
829 #define TXD_W0_RTS FIELD32(0x00000800)
830 #define TXD_W0_IFS FIELD32(0x00006000)
831 #define TXD_W0_RETRY_MODE FIELD32(0x00008000)
832 #define TXD_W0_AGC FIELD32(0x00ff0000)
833 #define TXD_W0_R2 FIELD32(0xff000000)
838 #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
843 #define TXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
844 #define TXD_W2_DATABYTE_COUNT FIELD32(0xffff0000)
850 #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff)
851 #define TXD_W3_PLCP_SIGNAL_REGNUM FIELD32(0x00007f00)
852 #define TXD_W3_PLCP_SIGNAL_BUSY FIELD32(0x00008000)
853 #define TXD_W3_PLCP_SERVICE FIELD32(0x00ff0000)
854 #define TXD_W3_PLCP_SERVICE_REGNUM FIELD32(0x7f000000)
855 #define TXD_W3_PLCP_SERVICE_BUSY FIELD32(0x80000000)
857 #define TXD_W4_PLCP_LENGTH_LOW FIELD32(0x000000ff)
858 #define TXD_W3_PLCP_LENGTH_LOW_REGNUM FIELD32(0x00007f00)
859 #define TXD_W3_PLCP_LENGTH_LOW_BUSY FIELD32(0x00008000)
860 #define TXD_W4_PLCP_LENGTH_HIGH FIELD32(0x00ff0000)
861 #define TXD_W3_PLCP_LENGTH_HIGH_REGNUM FIELD32(0x7f000000)
862 #define TXD_W3_PLCP_LENGTH_HIGH_BUSY FIELD32(0x80000000)
867 #define TXD_W5_BBCR4 FIELD32(0x0000ffff)
868 #define TXD_W5_AGC_REG FIELD32(0x007f0000)
869 #define TXD_W5_AGC_REG_VALID FIELD32(0x00800000)
870 #define TXD_W5_XXX_REG FIELD32(0x7f000000)
871 #define TXD_W5_XXX_REG_VALID FIELD32(0x80000000)
876 #define TXD_W6_SK_BUFF FIELD32(0xffffffff)
881 #define TXD_W7_RESERVED FIELD32(0xffffffff)
890 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
891 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
892 #define RXD_W0_MULTICAST FIELD32(0x00000004)
893 #define RXD_W0_BROADCAST FIELD32(0x00000008)
894 #define RXD_W0_MY_BSS FIELD32(0x00000010)
895 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
896 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
897 #define RXD_W0_DATABYTE_COUNT FIELD32(0xffff0000)
902 #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
907 #define RXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
908 #define RXD_W2_BBR0 FIELD32(0x00ff0000)
909 #define RXD_W2_SIGNAL FIELD32(0xff000000)
914 #define RXD_W3_RSSI FIELD32(0x000000ff)
915 #define RXD_W3_BBR3 FIELD32(0x0000ff00)
916 #define RXD_W3_BBR4 FIELD32(0x00ff0000)
917 #define RXD_W3_BBR5 FIELD32(0xff000000)
922 #define RXD_W4_RX_END_TIME FIELD32(0xffffffff)
927 #define RXD_W5_RESERVED FIELD32(0xffffffff)
928 #define RXD_W6_RESERVED FIELD32(0xffffffff)
929 #define RXD_W7_RESERVED FIELD32(0xffffffff)