Lines Matching refs:rt2x00dev
58 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
63 mutex_lock(&rt2x00dev->csr_mutex);
69 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
76 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
79 mutex_unlock(&rt2x00dev->csr_mutex);
82 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
87 mutex_lock(&rt2x00dev->csr_mutex);
97 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
103 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
105 WAIT_FOR_BBP(rt2x00dev, ®);
110 mutex_unlock(&rt2x00dev->csr_mutex);
113 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
118 mutex_lock(&rt2x00dev->csr_mutex);
124 if (WAIT_FOR_RF(rt2x00dev, ®)) {
131 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
132 rt2x00_rf_write(rt2x00dev, word, value);
135 mutex_unlock(&rt2x00dev->csr_mutex);
140 struct rt2x00_dev *rt2x00dev = eeprom->data;
143 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
155 struct rt2x00_dev *rt2x00dev = eeprom->data;
165 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
203 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
207 rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
220 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
227 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
238 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
241 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
246 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
250 led->rt2x00dev = rt2x00dev;
261 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
271 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
282 !rt2x00dev->intf_ap_count);
284 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
287 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
300 rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
302 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
307 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
311 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
315 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
319 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
323 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
334 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
339 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
341 rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
345 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
347 rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
351 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
353 rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
357 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
359 rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
363 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
365 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
367 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
369 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
371 rt2x00pci_register_read(rt2x00dev, CSR12, ®);
374 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
376 rt2x00pci_register_read(rt2x00dev, CSR18, ®);
379 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
381 rt2x00pci_register_read(rt2x00dev, CSR19, ®);
384 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
387 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
400 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
401 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
435 rt2400pci_bbp_write(rt2x00dev, 4, r4);
436 rt2400pci_bbp_write(rt2x00dev, 1, r1);
439 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
448 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
449 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
450 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
455 if (rt2x00_rf(rt2x00dev, RF2420))
463 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
464 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
465 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
469 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
470 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
471 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
481 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
482 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
487 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
490 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
492 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
495 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
500 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
505 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
508 static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
517 rt2x00pci_register_read(rt2x00dev, CSR20, ®);
519 (rt2x00dev->beacon_int - 20) * 16);
525 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
528 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
530 rt2x00pci_register_read(rt2x00dev, CSR20, ®);
532 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
535 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
538 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
543 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
545 rt2400pci_config_txpower(rt2x00dev,
548 rt2400pci_config_retry_limit(rt2x00dev, libconf);
550 rt2400pci_config_ps(rt2x00dev, libconf);
553 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
558 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
561 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
567 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
576 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
582 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
586 static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
590 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
596 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
599 rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
602 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
616 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
618 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
667 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
675 rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
676 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
677 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
678 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
679 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
680 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
682 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
683 rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
686 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
688 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
689 rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
692 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
694 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
695 rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
698 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
700 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
701 rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
704 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
706 rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
707 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
708 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
709 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
711 entry_priv = rt2x00dev->rx->entries[0].priv_data;
712 rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
715 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
720 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
724 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
725 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
726 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
727 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
729 rt2x00pci_register_read(rt2x00dev, TIMECSR, ®);
733 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
735 rt2x00pci_register_read(rt2x00dev, CSR9, ®);
737 (rt2x00dev->rx->data_size / 128));
738 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
740 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
749 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
751 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
753 rt2x00pci_register_read(rt2x00dev, ARCSR0, ®);
758 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
760 rt2x00pci_register_read(rt2x00dev, RXCSR3, ®);
767 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
769 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
771 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
774 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
775 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
777 rt2x00pci_register_read(rt2x00dev, MACCSR2, ®);
779 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
781 rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®);
786 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
788 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
792 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
794 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
797 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
804 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
805 rt2x00pci_register_read(rt2x00dev, CNT4, ®);
810 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
816 rt2400pci_bbp_read(rt2x00dev, 0, &value);
822 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
826 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
833 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
836 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
837 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
838 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
839 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
840 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
841 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
842 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
843 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
844 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
845 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
846 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
847 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
848 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
849 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
852 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
857 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
867 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
872 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
876 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
879 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
891 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
892 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
899 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
905 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
908 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
913 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
914 rt2400pci_init_registers(rt2x00dev) ||
915 rt2400pci_init_bbp(rt2x00dev)))
921 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
926 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
929 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
940 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
945 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
953 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®2);
958 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
965 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
972 retval = rt2400pci_enable_radio(rt2x00dev);
975 rt2400pci_disable_radio(rt2x00dev);
981 rt2400pci_toggle_rx(rt2x00dev, state);
987 rt2400pci_toggle_irq(rt2x00dev, state);
993 retval = rt2400pci_set_state(rt2x00dev, state);
1001 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1010 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1083 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1090 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
1092 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1094 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1099 rt2400pci_write_tx_desc(rt2x00dev, entry->skb, txdesc);
1104 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1112 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1115 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1120 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
1124 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1127 static void rt2400pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1133 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1135 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
1137 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1147 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1176 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1191 entry->queue->rt2x00dev->rssi_offset;
1202 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1205 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1243 struct rt2x00_dev *rt2x00dev = dev_instance;
1244 u32 reg = rt2x00dev->irqvalue[0];
1256 rt2x00lib_beacondone(rt2x00dev);
1262 rt2x00pci_rxdone(rt2x00dev);
1268 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1274 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1280 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1283 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1290 struct rt2x00_dev *rt2x00dev = dev_instance;
1297 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
1298 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1303 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1307 rt2x00dev->irqvalue[0] = reg;
1310 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1319 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1326 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
1328 eeprom.data = rt2x00dev;
1338 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1344 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1347 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1350 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1352 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1359 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1368 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1374 rt2x00pci_register_read(rt2x00dev, CSR0, ®);
1375 rt2x00_set_chip(rt2x00dev, RT2460, value,
1378 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
1379 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1386 rt2x00dev->default_ant.tx =
1388 rt2x00dev->default_ant.rx =
1397 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1398 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1399 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1400 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1408 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1412 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1420 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1426 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
1452 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1454 struct hw_mode_spec *spec = &rt2x00dev->spec;
1462 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1467 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1468 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1469 rt2x00_eeprom_addr(rt2x00dev,
1490 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1499 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1506 retval = rt2400pci_validate_eeprom(rt2x00dev);
1510 retval = rt2400pci_init_eeprom(rt2x00dev);
1517 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1524 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1525 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1530 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1541 struct rt2x00_dev *rt2x00dev = hw->priv;
1557 rt2400pci_config_cw(rt2x00dev,
1558 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1565 struct rt2x00_dev *rt2x00dev = hw->priv;
1569 rt2x00pci_register_read(rt2x00dev, CSR17, ®);
1571 rt2x00pci_register_read(rt2x00dev, CSR16, ®);
1579 struct rt2x00_dev *rt2x00dev = hw->priv;
1582 rt2x00pci_register_read(rt2x00dev, CSR15, ®);