Lines Matching defs:txq_id
464 static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
467 (index & 0xff) | (txq_id << 8));
468 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
482 int txq_id = txq->q.id;
485 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
488 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
499 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1536 int txq_id = txq->q.id;
1545 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
1549 scd_bc_tbl[txq_id].
1706 u16 txq_id)
1711 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
1717 * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
1720 static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1723 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1725 <= txq_id)) {
1728 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1734 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1736 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1738 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1739 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1741 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1743 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1744 iwl_txq_ctx_deactivate(priv, txq_id);
1745 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1754 u16 txq_id)
1763 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
1767 if (txq_id & 0x1)
1781 * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
1784 static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1791 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1793 <= txq_id)) {
1796 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1812 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1815 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1818 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1822 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1823 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1824 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1828 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
1833 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1837 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1840 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1888 int txq_id, u16 start_idx)
1914 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb);
1936 txq_id = SEQ_TO_QUEUE(seq);
1942 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1943 agg->frame_count, txq_id, idx);
1945 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1949 " idx=%d, txq_id=%d\n", idx, txq_id);
2058 int txq_id = SEQ_TO_QUEUE(sequence);
2060 struct iwl_tx_queue *txq = &priv->txq[txq_id];
2072 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
2073 "is out of range [0-%d] %d %d\n", txq_id,
2082 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
2102 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
2112 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
2121 iwl_wake_queue(priv, txq_id);
2135 txq_id,
2140 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
2148 iwl_wake_queue(priv, txq_id);
2151 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);