Lines Matching refs:txq_id
270 int txq_id, int index)
272 struct iwl_tx_queue *txq = &priv->txq[txq_id];
276 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
287 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
288 (txq_id != IWL_CMD_QUEUE_NUM) &&
290 iwl_wake_queue(priv, txq_id);
301 int txq_id = SEQ_TO_QUEUE(sequence);
303 struct iwl_tx_queue *txq = &priv->txq[txq_id];
311 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
312 "is out of range [0-%d] %d %d\n", txq_id,
336 txq_id, iwl3945_get_tx_fail_reason(status), status,
340 iwl3945_tx_queue_reclaim(priv, txq_id, index);
891 int txq_id, slots_num;
906 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
907 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
909 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
910 txq_id);
912 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1064 int txq_id;
1068 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1069 txq_id++)
1070 if (txq_id == IWL_CMD_QUEUE_NUM)
1073 iwl_tx_queue_free(priv, txq_id);
1081 int txq_id;
1088 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1089 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1091 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
2226 int txq_id = txq->q.id;
2230 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2232 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2233 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2235 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),