Lines Matching refs:b43_phy_mask
221 b43_phy_mask(dev, B43_LPPHY_AFE_DAC_CTL, 0xF7FF);
235 b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE);
341 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
343 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
344 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
431 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
432 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
446 b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
480 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
482 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
689 b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
774 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
776 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFF7);
780 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF);
782 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF);
786 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F);
788 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF);
792 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF);
793 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF);
802 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80);
803 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00);
810 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
811 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
812 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
814 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
816 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
817 b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7);
820 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
843 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
845 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F);
846 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF);
848 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF);
980 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD);
981 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF);
988 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80);
989 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF);
995 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB);
1005 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7);
1008 b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF);
1049 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
1177 b43_phy_mask(dev, B43_PHY_OFDM(0xD0), 0xFFFD);
1429 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x83FF);
1431 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0x80FF);
1432 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xDFFF);
1435 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xE0FF);
1437 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFCFF);
1441 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xE0FF);
1443 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xF7F7);
1445 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFE7);
1472 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFC7);
1500 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xEFFF);
1503 b43_phy_mask(dev, B43_PHY_OFDM(0x103), 0xFFFE);
1510 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF);
1515 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF);
1522 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xEFFF);
1535 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF);
1712 b43_phy_mask(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF);
1810 b43_phy_mask(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000);
1920 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE);
1921 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
1933 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFC);
1934 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7);
1935 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFDF);
1943 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE);
1944 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xF7FF);
2689 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xfff8);