Lines Matching defs:ah
20 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
23 ath_print(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
25 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
26 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
27 ah->txurn_interrupt_mask);
29 ENABLE_REGWRITE_BUFFER(ah);
31 REG_WRITE(ah, AR_IMR_S0,
32 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
33 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
34 REG_WRITE(ah, AR_IMR_S1,
35 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
36 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
38 ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
39 ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
40 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
42 REGWRITE_BUFFER_FLUSH(ah);
43 DISABLE_REGWRITE_BUFFER(ah);
46 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
48 return REG_READ(ah, AR_QTXDP(q));
52 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
54 REG_WRITE(ah, AR_QTXDP(q), txdp);
58 void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
60 ath_print(ath9k_hw_common(ah), ATH_DBG_QUEUE,
62 REG_WRITE(ah, AR_Q_TXE, 1 << q);
66 void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
78 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
82 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
85 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
96 * @ah: atheros hardware struct
118 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
123 if (ah->tx_trig_level >= ah->config.max_txtrig_level)
126 omask = ath9k_hw_set_interrupts(ah, ah->imask & ~ATH9K_INT_GLOBAL);
128 txcfg = REG_READ(ah, AR_TXCFG);
132 if (curLevel < ah->config.max_txtrig_level)
137 REG_WRITE(ah, AR_TXCFG,
140 ath9k_hw_set_interrupts(ah, omask);
142 ah->tx_trig_level = newLevel;
148 bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
152 struct ath_common *common = ath9k_hw_common(ah);
153 struct ath9k_hw_capabilities *pCap = &ah->caps;
164 qi = &ah->txq[q];
171 REG_WRITE(ah, AR_Q_TXD, 1 << q);
174 if (ath9k_hw_numtxpending(ah, q) == 0)
179 if (ath9k_hw_numtxpending(ah, q)) {
182 __func__, ath9k_hw_numtxpending(ah, q), q);
185 tsfLow = REG_READ(ah, AR_TSF_L32);
186 REG_WRITE(ah, AR_QUIET2,
188 REG_WRITE(ah, AR_QUIET_PERIOD, 100);
189 REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
190 REG_SET_BIT(ah, AR_TIMER_MODE,
193 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
201 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
204 REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
207 while (ath9k_hw_numtxpending(ah, q)) {
217 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
220 REG_WRITE(ah, AR_Q_TXD, 0);
228 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
230 *txqs &= ah->intr_txqs;
231 ah->intr_txqs &= ~(*txqs);
235 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
239 struct ath_common *common = ath9k_hw_common(ah);
240 struct ath9k_hw_capabilities *pCap = &ah->caps;
249 qi = &ah->txq[q];
307 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
310 struct ath_common *common = ath9k_hw_common(ah);
311 struct ath9k_hw_capabilities *pCap = &ah->caps;
320 qi = &ah->txq[q];
346 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
349 struct ath_common *common = ath9k_hw_common(ah);
351 struct ath9k_hw_capabilities *pCap = &ah->caps;
369 if (ah->txq[q].tqi_type ==
386 qi = &ah->txq[q];
407 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
414 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
416 struct ath9k_hw_capabilities *pCap = &ah->caps;
417 struct ath_common *common = ath9k_hw_common(ah);
425 qi = &ah->txq[q];
435 ah->txok_interrupt_mask &= ~(1 << q);
436 ah->txerr_interrupt_mask &= ~(1 << q);
437 ah->txdesc_interrupt_mask &= ~(1 << q);
438 ah->txeol_interrupt_mask &= ~(1 << q);
439 ah->txurn_interrupt_mask &= ~(1 << q);
440 ath9k_hw_set_txq_interrupts(ah, qi);
446 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
448 struct ath9k_hw_capabilities *pCap = &ah->caps;
449 struct ath_common *common = ath9k_hw_common(ah);
450 struct ath9k_channel *chan = ah->curchan;
460 qi = &ah->txq[q];
479 ENABLE_REGWRITE_BUFFER(ah);
481 REG_WRITE(ah, AR_DLCL_IFS(q),
486 REG_WRITE(ah, AR_DRETRY_LIMIT(q),
491 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
492 REG_WRITE(ah, AR_DMISC(q),
495 REGWRITE_BUFFER_FLUSH(ah);
498 REG_WRITE(ah, AR_QCBRCFG(q),
501 REG_WRITE(ah, AR_QMISC(q),
502 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR |
507 REG_WRITE(ah, AR_QRDYTIMECFG(q),
512 REGWRITE_BUFFER_FLUSH(ah);
514 REG_WRITE(ah, AR_DCHNTIME(q),
520 REG_WRITE(ah, AR_QMISC(q),
521 REG_READ(ah, AR_QMISC(q)) |
527 REG_WRITE(ah, AR_DMISC(q),
528 REG_READ(ah, AR_DMISC(q)) |
532 REGWRITE_BUFFER_FLUSH(ah);
533 DISABLE_REGWRITE_BUFFER(ah);
536 REG_WRITE(ah, AR_DMISC(q),
537 REG_READ(ah, AR_DMISC(q)) |
542 ENABLE_REGWRITE_BUFFER(ah);
544 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
549 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
555 REGWRITE_BUFFER_FLUSH(ah);
556 DISABLE_REGWRITE_BUFFER(ah);
563 if (AR_SREV_9300_20_OR_LATER(ah) &&
564 ah->opmode != NL80211_IFTYPE_ADHOC) {
565 REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
571 ENABLE_REGWRITE_BUFFER(ah);
573 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
578 (ah->config.sw_beacon_response_time -
579 ah->config.dma_beacon_response_time) -
580 ah->config.additional_swba_backoff) * 1024;
581 REG_WRITE(ah, AR_QRDYTIMECFG(q),
583 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
587 REGWRITE_BUFFER_FLUSH(ah);
588 DISABLE_REGWRITE_BUFFER(ah);
592 REG_WRITE(ah, AR_QMISC(q),
593 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
596 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
604 REG_WRITE(ah, AR_DMISC(q),
605 REG_READ(ah, AR_DMISC(q)) |
611 if (AR_SREV_9300_20_OR_LATER(ah))
612 REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
615 ah->txok_interrupt_mask |= 1 << q;
617 ah->txok_interrupt_mask &= ~(1 << q);
619 ah->txerr_interrupt_mask |= 1 << q;
621 ah->txerr_interrupt_mask &= ~(1 << q);
623 ah->txdesc_interrupt_mask |= 1 << q;
625 ah->txdesc_interrupt_mask &= ~(1 << q);
627 ah->txeol_interrupt_mask |= 1 << q;
629 ah->txeol_interrupt_mask &= ~(1 << q);
631 ah->txurn_interrupt_mask |= 1 << q;
633 ah->txurn_interrupt_mask &= ~(1 << q);
634 ath9k_hw_set_txq_interrupts(ah, qi);
640 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
686 rs->rs_rate = RXSTATUS_RATE(ah, (&ads));
731 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
736 REG_SET_BIT(ah, AR_DIAG_SW,
739 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
741 REG_CLR_BIT(ah, AR_DIAG_SW,
745 reg = REG_READ(ah, AR_OBS_BUS_1);
746 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
753 REG_CLR_BIT(ah, AR_DIAG_SW,
761 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
763 REG_WRITE(ah, AR_RXDP, rxdp);
767 void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
769 ath9k_enable_mib_counters(ah);
771 ath9k_ani_reset(ah, is_scanning);
773 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
777 void ath9k_hw_stoppcurecv(struct ath_hw *ah)
779 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
781 ath9k_hw_disable_mib_counters(ah);
785 void ath9k_hw_abortpcurecv(struct ath_hw *ah)
787 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
789 ath9k_hw_disable_mib_counters(ah);
793 bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
797 struct ath_common *common = ath9k_hw_common(ah);
800 REG_WRITE(ah, AR_CR, AR_CR_RXD);
804 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
814 REG_READ(ah, AR_CR),
815 REG_READ(ah, AR_DIAG_SW));
826 int ath9k_hw_beaconq_setup(struct ath_hw *ah)
835 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
839 bool ath9k_hw_intrpend(struct ath_hw *ah)
843 if (AR_SREV_9100(ah))
846 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
850 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
859 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
862 enum ath9k_int omask = ah->imask;
864 struct ath9k_hw_capabilities *pCap = &ah->caps;
865 struct ath_common *common = ath9k_hw_common(ah);
871 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
872 (void) REG_READ(ah, AR_IER);
873 if (!AR_SREV_9100(ah)) {
874 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
875 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
877 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
878 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
887 if (ah->config.tx_intr_mitigation)
890 if (ah->txok_interrupt_mask)
892 if (ah->txdesc_interrupt_mask)
895 if (ah->txerr_interrupt_mask)
897 if (ah->txeol_interrupt_mask)
901 if (AR_SREV_9300_20_OR_LATER(ah)) {
903 if (ah->config.rx_intr_mitigation) {
910 if (ah->config.rx_intr_mitigation)
942 REG_WRITE(ah, AR_IMR, mask);
943 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
946 ah->imrs2_reg |= mask2;
947 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
951 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
953 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
958 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
959 if (!AR_SREV_9100(ah)) {
960 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
962 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
965 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
967 REG_WRITE(ah, AR_INTR_SYNC_MASK,
971 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));