Lines Matching defs:ah
53 static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
57 struct ath9k_hw_capabilities *pCap = &ah->caps;
59 struct ath_common *common = ath9k_hw_common(ah);
61 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
62 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
64 isr = REG_READ(ah, AR_ISR);
67 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
77 isr2 = REG_READ(ah, AR_ISR_S2);
97 REG_WRITE(ah, AR_ISR_S2, isr2);
103 isr = REG_READ(ah, AR_ISR_RAC);
112 if (ah->config.rx_intr_mitigation)
116 if (ah->config.tx_intr_mitigation)
131 s0 = REG_READ(ah, AR_ISR_S0);
132 REG_WRITE(ah, AR_ISR_S0, s0);
133 s1 = REG_READ(ah, AR_ISR_S1);
134 REG_WRITE(ah, AR_ISR_S1, s1);
145 s5 = REG_READ(ah, AR_ISR_S5_S);
147 s5 = REG_READ(ah, AR_ISR_S5);
149 ah->intr_gen_timer_trigger =
152 ah->intr_gen_timer_thresh =
155 if (ah->intr_gen_timer_trigger)
159 REG_WRITE(ah, AR_ISR_S5, s5);
168 REG_WRITE(ah, AR_ISR, isr);
170 (void) REG_READ(ah, AR_ISR);
174 ar9003_hw_bb_watchdog_read(ah);
179 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
180 REG_WRITE(ah, AR_RC, 0);
188 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
189 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
195 static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
235 static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
240 ads = &ah->ts_ring[ah->ts_tail];
245 ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
249 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
268 ath9k_hw_updatetxtriglevel(ah, true);
279 ath9k_hw_updatetxtriglevel(ah, true);
283 ath9k_hw_updatetxtriglevel(ah, true);
312 static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
318 if (txpower > ah->txpower_limit)
319 txpower = ah->txpower_limit;
321 txpower += ah->txpower_indexoffset;
350 static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
406 static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
417 static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
435 static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
444 static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
451 static void ar9003_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
461 static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
472 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains)
500 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
502 REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
506 void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
510 REG_WRITE(ah, AR_HP_RXDP, rxdp);
512 REG_WRITE(ah, AR_LP_RXDP, rxdp);
516 int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
625 void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
627 ah->ts_tail = 0;
629 memset((void *) ah->ts_ring, 0,
630 ah->ts_size * sizeof(struct ar9003_txs));
632 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
634 ah->ts_paddr_start, ah->ts_paddr_end,
635 ah->ts_ring, ah->ts_size);
637 REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
638 REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
641 void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
646 ah->ts_paddr_start = ts_paddr_start;
647 ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs));
648 ah->ts_size = size;
649 ah->ts_ring = (struct ar9003_txs *) ts_start;
651 ath9k_hw_reset_txstatus_ring(ah);