Lines Matching defs:ah
47 * @ah: atheros hardware structure
66 static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
73 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
88 if (AR_SREV_9287_11_OR_LATER(ah)) {
91 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
94 REG_WRITE_ARRAY(&ah->iniCckfirNormal,
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
112 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
132 REG_RMW_FIELD(ah, AR_AN_SYNTH9,
149 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
151 ah->curchan = chan;
152 ah->curchan_rad_index = -1;
159 * @ah: atheros hardware structure
165 static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
197 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
200 ah->config.spurmode = SPUR_ENABLE_EEPROM;
202 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
227 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
231 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
237 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
239 ENABLE_REGWRITE_BUFFER(ah);
245 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
252 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
282 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
285 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
303 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
304 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
336 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
337 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
347 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
348 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
358 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
359 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
369 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
370 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
380 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
381 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
391 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
392 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
402 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
403 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
413 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
414 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
416 REGWRITE_BUFFER_FLUSH(ah);
417 DISABLE_REGWRITE_BUFFER(ah);
420 static void ar9002_olc_init(struct ath_hw *ah)
428 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
430 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
437 ah->originalGain[i] =
438 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
440 ah->PDADCdelta = 0;
444 static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
457 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
459 else if (AR_SREV_9280_20(ah))
470 static void ar9002_hw_do_getnf(struct ath_hw *ah,
475 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
478 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
479 if (IS_CHAN_HT40(ah->curchan))
482 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
485 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
488 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
489 if (IS_CHAN_HT40(ah->curchan))
493 static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
495 if (AR_SREV_9285(ah)) {
496 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
497 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
498 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
499 } else if (AR_SREV_9287(ah)) {
500 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
501 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
502 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
503 } else if (AR_SREV_9271(ah)) {
504 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ;
505 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ;
506 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9271_2GHZ;
508 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ;
509 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ;
510 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ;
511 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ;
512 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ;
513 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ;
517 void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
519 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
530 ar9002_hw_set_nf_limits(ah);