Lines Matching defs:ah
23 static void ar9002_hw_setup_calibration(struct ath_hw *ah,
26 struct ath_common *common = ath9k_hw_common(ah);
28 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
34 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
39 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
44 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
49 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
57 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
61 static bool ar9002_hw_per_calibration(struct ath_hw *ah,
66 struct ath9k_hw_cal_data *caldata = ah->caldata;
70 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
73 currCal->calData->calCollect(ah);
74 ah->cal_samples++;
76 if (ah->cal_samples >=
84 currCal->calData->calPostProc(ah, numChains);
89 ar9002_hw_setup_calibration(ah, currCal);
93 ath9k_hw_reset_calibration(ah, currCal);
100 static bool ar9002_hw_iscal_supported(struct ath_hw *ah,
103 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
105 switch (calType & ah->supp_cals) {
118 static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
123 ah->totalPowerMeasI[i] +=
124 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
125 ah->totalPowerMeasQ[i] +=
126 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
127 ah->totalIqCorrMeas[i] +=
128 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
129 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
131 ah->cal_samples, i, ah->totalPowerMeasI[i],
132 ah->totalPowerMeasQ[i],
133 ah->totalIqCorrMeas[i]);
137 static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
142 ah->totalAdcIOddPhase[i] +=
143 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
144 ah->totalAdcIEvenPhase[i] +=
145 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
146 ah->totalAdcQOddPhase[i] +=
147 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
148 ah->totalAdcQEvenPhase[i] +=
149 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
151 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
154 ah->cal_samples, i,
155 ah->totalAdcIOddPhase[i],
156 ah->totalAdcIEvenPhase[i],
157 ah->totalAdcQOddPhase[i],
158 ah->totalAdcQEvenPhase[i]);
162 static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
167 ah->totalAdcDcOffsetIOddPhase[i] +=
168 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
169 ah->totalAdcDcOffsetIEvenPhase[i] +=
170 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
171 ah->totalAdcDcOffsetQOddPhase[i] +=
172 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
173 ah->totalAdcDcOffsetQEvenPhase[i] +=
174 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
176 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
179 ah->cal_samples, i,
180 ah->totalAdcDcOffsetIOddPhase[i],
181 ah->totalAdcDcOffsetIEvenPhase[i],
182 ah->totalAdcDcOffsetQOddPhase[i],
183 ah->totalAdcDcOffsetQEvenPhase[i]);
187 static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
189 struct ath_common *common = ath9k_hw_common(ah);
196 powerMeasI = ah->totalPowerMeasI[i];
197 powerMeasQ = ah->totalPowerMeasQ[i];
198 iqCorrMeas = ah->totalIqCorrMeas[i];
206 i, ah->totalIqCorrMeas[i]);
249 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
252 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
261 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
265 static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
267 struct ath_common *common = ath9k_hw_common(ah);
272 iOddMeasOffset = ah->totalAdcIOddPhase[i];
273 iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
274 qOddMeasOffset = ah->totalAdcQOddPhase[i];
275 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
308 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
311 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
318 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
319 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
323 static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
325 struct ath_common *common = ath9k_hw_common(ah);
329 ah->cal_list_curr->calData;
334 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
335 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
336 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
337 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
367 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
370 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
376 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
377 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
381 static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah)
386 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
389 if (ah->initPDADC == 0 || currPDADC == 0) {
397 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
402 delta = ((currPDADC - ah->initPDADC)*4) / slope;
404 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
406 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
411 static void ar9280_hw_olc_temp_compensation(struct ath_hw *ah)
416 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
419 if (ah->initPDADC == 0 || currPDADC == 0)
422 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
423 delta = (currPDADC - ah->initPDADC + 4) / 8;
425 delta = (currPDADC - ah->initPDADC + 5) / 10;
427 if (delta != ah->PDADCdelta) {
428 ah->PDADCdelta = delta;
430 regval = ah->originalGain[i] - delta;
434 REG_RMW_FIELD(ah,
441 static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
457 regList[i][1] = REG_READ(ah, regList[i][0]);
459 regVal = REG_READ(ah, 0x7834);
461 REG_WRITE(ah, 0x7834, regVal);
462 regVal = REG_READ(ah, 0x9808);
464 REG_WRITE(ah, 0x9808, regVal);
467 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
469 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
471 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
473 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
475 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
477 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
479 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
481 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
483 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
485 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
487 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
492 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
494 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
500 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
502 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
506 regVal = REG_READ(ah, 0x7834);
508 REG_WRITE(ah, 0x7834, regVal);
510 /* regVal = REG_READ(ah, 0x7834); */
512 regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
514 REG_WRITE(ah, 0x7834, regVal);
520 if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
521 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
522 ah->pacal_info.max_skipcount =
523 2 * ah->pacal_info.max_skipcount;
524 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
526 ah->pacal_info.max_skipcount = 1;
527 ah->pacal_info.skipcount = 0;
528 ah->pacal_info.prev_offset = regVal;
531 ENABLE_REGWRITE_BUFFER(ah);
533 regVal = REG_READ(ah, 0x7834);
535 REG_WRITE(ah, 0x7834, regVal);
536 regVal = REG_READ(ah, 0x9808);
538 REG_WRITE(ah, 0x9808, regVal);
541 REG_WRITE(ah, regList[i][0], regList[i][1]);
543 REGWRITE_BUFFER_FLUSH(ah);
544 DISABLE_REGWRITE_BUFFER(ah);
547 static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
549 struct ath_common *common = ath9k_hw_common(ah);
566 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
570 if (AR_SREV_9285_11(ah)) {
571 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
576 regList[i][1] = REG_READ(ah, regList[i][0]);
578 regVal = REG_READ(ah, 0x7834);
580 REG_WRITE(ah, 0x7834, regVal);
581 regVal = REG_READ(ah, 0x9808);
583 REG_WRITE(ah, 0x9808, regVal);
585 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
586 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
587 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
588 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
589 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
590 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
591 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
592 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
593 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
594 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
595 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
596 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
597 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
598 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
600 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
602 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
603 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
606 regVal = REG_READ(ah, 0x7834);
608 REG_WRITE(ah, 0x7834, regVal);
610 regVal = REG_READ(ah, 0x7834);
612 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
614 REG_WRITE(ah, 0x7834, regVal);
617 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
619 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
620 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
621 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
622 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
629 if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
630 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
631 ah->pacal_info.max_skipcount =
632 2 * ah->pacal_info.max_skipcount;
633 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
635 ah->pacal_info.max_skipcount = 1;
636 ah->pacal_info.skipcount = 0;
637 ah->pacal_info.prev_offset = offset;
640 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
641 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
643 regVal = REG_READ(ah, 0x7834);
645 REG_WRITE(ah, 0x7834, regVal);
646 regVal = REG_READ(ah, 0x9808);
648 REG_WRITE(ah, 0x9808, regVal);
651 REG_WRITE(ah, regList[i][0], regList[i][1]);
653 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
655 if (AR_SREV_9285_11(ah))
656 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
660 static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
662 if (AR_SREV_9271(ah)) {
663 if (is_reset || !ah->pacal_info.skipcount)
664 ar9271_hw_pa_cal(ah, is_reset);
666 ah->pacal_info.skipcount--;
667 } else if (AR_SREV_9285_11_OR_LATER(ah)) {
668 if (is_reset || !ah->pacal_info.skipcount)
669 ar9285_hw_pa_cal(ah, is_reset);
671 ah->pacal_info.skipcount--;
675 static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah)
678 ar9287_hw_olc_temp_compensation(ah);
680 ar9280_hw_olc_temp_compensation(ah);
683 static bool ar9002_hw_calibrate(struct ath_hw *ah,
689 struct ath9k_cal_list *currCal = ah->cal_list_curr;
692 nfcal = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF);
693 if (ah->caldata)
694 nfcal_pending = ah->caldata->nfcal_pending;
699 iscaldone = ar9002_hw_per_calibration(ah, chan,
702 ah->cal_list_curr = currCal = currCal->calNext;
706 ath9k_hw_reset_calibration(ah, currCal);
717 if (ath9k_hw_getnf(ah, chan)) {
724 ath9k_hw_loadnf(ah, ah->curchan);
728 ath9k_hw_start_nfcal(ah, false);
730 ar9002_hw_pa_cal(ah, false);
731 ar9002_hw_olc_temp_compensation(ah);
739 static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
741 struct ath_common *common = ath9k_hw_common(ah);
743 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
745 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
746 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
747 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
749 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
750 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
751 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
758 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
759 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
760 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
762 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
763 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
764 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
765 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
766 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
773 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
774 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
775 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
780 static bool ar9285_hw_clc(struct ath_hw *ah, struct ath9k_channel *chan)
792 if (!(ar9285_hw_cl_cal(ah, chan)))
795 txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
799 clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
808 reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
810 reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
820 reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
821 if (AR_SREV_9285E_20(ah)) {
822 REG_WRITE(ah, AR9285_RF2G5,
826 REG_WRITE(ah, AR9285_RF2G5,
830 retv = ar9285_hw_cl_cal(ah, chan);
831 REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
836 static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
838 struct ath_common *common = ath9k_hw_common(ah);
840 if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
841 if (!ar9285_hw_clc(ah, chan))
844 if (AR_SREV_9280_10_OR_LATER(ah)) {
845 if (!AR_SREV_9287_10_OR_LATER(ah))
846 REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
848 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
853 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
854 REG_READ(ah, AR_PHY_AGC_CONTROL) |
858 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
867 if (AR_SREV_9280_10_OR_LATER(ah)) {
868 if (!AR_SREV_9287_10_OR_LATER(ah))
869 REG_SET_BIT(ah, AR_PHY_ADC_CTL,
871 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
877 ar9002_hw_pa_cal(ah, true);
880 ath9k_hw_start_nfcal(ah, true);
882 if (ah->caldata)
883 ah->caldata->nfcal_pending = true;
885 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
888 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
889 if (ar9002_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
890 INIT_CAL(&ah->adcgain_caldata);
891 INSERT_CAL(ah, &ah->adcgain_caldata);
895 if (ar9002_hw_iscal_supported(ah, ADC_DC_CAL)) {
896 INIT_CAL(&ah->adcdc_caldata);
897 INSERT_CAL(ah, &ah->adcdc_caldata);
901 if (ar9002_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
902 INIT_CAL(&ah->iq_caldata);
903 INSERT_CAL(ah, &ah->iq_caldata);
908 ah->cal_list_curr = ah->cal_list;
910 if (ah->cal_list_curr)
911 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
914 if (ah->caldata)
915 ah->caldata->CalValid = 0;
970 static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
972 if (AR_SREV_9100(ah)) {
973 ah->iq_caldata.calData = &iq_cal_multi_sample;
974 ah->supp_cals = IQ_MISMATCH_CAL;
978 if (AR_SREV_9160_10_OR_LATER(ah)) {
979 if (AR_SREV_9280_10_OR_LATER(ah)) {
980 ah->iq_caldata.calData = &iq_cal_single_sample;
981 ah->adcgain_caldata.calData =
983 ah->adcdc_caldata.calData =
985 ah->adcdc_calinitdata.calData =
988 ah->iq_caldata.calData = &iq_cal_multi_sample;
989 ah->adcgain_caldata.calData =
991 ah->adcdc_caldata.calData =
993 ah->adcdc_calinitdata.calData =
996 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
1000 void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
1002 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1003 struct ath_hw_ops *ops = ath9k_hw_ops(ah);