Lines Matching defs:ah
31 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
34 memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
41 int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
44 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
46 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
49 memcpy(&ah->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info));
55 ah->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
63 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
73 if (ah->ah_version == AR5K_AR5210) {
89 ah->ah_txq[queue].tqi_type !=
106 if (ah->ah_version != AR5K_AR5212)
107 ATH5K_ERR(ah->ah_sc,
120 memset(&ah->ah_txq[queue], 0, sizeof(struct ath5k_txq_info));
121 ah->ah_txq[queue].tqi_type = queue_type;
125 ret = ath5k_hw_set_tx_queueprops(ah, queue, queue_info);
135 AR5K_Q_ENABLE_BITS(ah->ah_txq_status, queue);
144 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
147 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
150 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
153 if (ah->ah_version == AR5K_AR5210)
156 pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue));
162 if (!pending && AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
171 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
173 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
177 ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
179 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
185 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
188 struct ath5k_txq_info *tq = &ah->ah_txq[queue];
190 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
192 tq = &ah->ah_txq[queue];
197 if (ah->ah_version == AR5K_AR5210) {
203 ath5k_hw_reg_write(ah, ah->ah_turbo ?
207 ath5k_hw_reg_write(ah, ah->ah_turbo ?
211 ath5k_hw_reg_write(ah, ah->ah_turbo ?
216 if (ah->ah_turbo) {
217 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
218 (ah->ah_aifs + tq->tqi_aifs) *
223 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS +
224 (ah->ah_aifs + tq->tqi_aifs) *
230 ath5k_hw_reg_write(ah, ah->ah_turbo ?
234 ath5k_hw_reg_write(ah, ah->ah_turbo ?
235 (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
237 (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
241 ath5k_hw_reg_write(ah, ah->ah_turbo ?
251 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN;
252 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX;
253 ah->ah_aifs = AR5K_TUNE_AIFS;
255 if (IS_CHAN_XR(ah->ah_current_channel) &&
256 ah->ah_version == AR5K_AR5212) {
257 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR;
258 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR;
259 ah->ah_aifs = AR5K_TUNE_AIFS_XR;
261 } else if (IS_CHAN_B(ah->ah_current_channel) &&
262 ah->ah_version != AR5K_AR5210) {
263 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B;
264 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B;
265 ah->ah_aifs = AR5K_TUNE_AIFS_11B;
269 while (cw_min < ah->ah_cw_min)
280 if (ah->ah_software_retry) {
281 retry_lg = ah->ah_limit_tx_retries;
290 if (ah->ah_version == AR5K_AR5210) {
291 ath5k_hw_reg_write(ah,
302 ath5k_hw_reg_write(ah,
317 ath5k_hw_reg_write(ah,
320 AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs,
328 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
332 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
336 if (ah->ah_mac_version < AR5K_SREV_AR5211)
337 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
341 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
346 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
349 AR5K_REG_ENABLE_BITS(ah,
356 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
362 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
369 AR5K_REG_ENABLE_BITS(ah,
375 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
379 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
387 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
392 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
401 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
406 ath5k_hw_reg_write(ah, ((tq->tqi_ready_time -
413 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
419 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
435 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
438 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
441 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
444 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
447 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
450 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrorn, queue);
453 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrurn, queue);
456 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_qtrig, queue);
459 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_nofrm, queue);
464 ah->ah_txq_imr_txok &= ah->ah_txq_status;
465 ah->ah_txq_imr_txerr &= ah->ah_txq_status;
466 ah->ah_txq_imr_txurn &= ah->ah_txq_status;
467 ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
468 ah->ah_txq_imr_txeol &= ah->ah_txq_status;
469 ah->ah_txq_imr_cbrorn &= ah->ah_txq_status;
470 ah->ah_txq_imr_cbrurn &= ah->ah_txq_status;
471 ah->ah_txq_imr_qtrig &= ah->ah_txq_status;
472 ah->ah_txq_imr_nofrm &= ah->ah_txq_status;
474 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
476 AR5K_REG_SM(ah->ah_txq_imr_txdesc,
478 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
480 AR5K_REG_SM(ah->ah_txq_imr_txeol,
483 AR5K_REG_DISABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN);
484 AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2,
485 AR5K_REG_SM(ah->ah_txq_imr_txurn,
487 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_cbrorn,
489 AR5K_REG_SM(ah->ah_txq_imr_cbrurn,
491 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_qtrig,
494 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_nofrm,
498 if (ah->ah_txq_imr_nofrm == 0)
499 ath5k_hw_reg_write(ah, 0, AR5K_TXNOFRM);
502 AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(queue), queue);
511 int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
513 u32 slot_time_clock = ath5k_hw_htoclock(ah, slot_time);
518 if (ah->ah_version == AR5K_AR5210)
519 ath5k_hw_reg_write(ah, slot_time_clock, AR5K_SLOT_TIME);
521 ath5k_hw_reg_write(ah, slot_time_clock, AR5K_DCU_GBL_IFS_SLOT);