Lines Matching defs:ah
41 * @ah: The &struct ath5k_hw
46 int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
48 struct ath_common *common = ath5k_hw_common(ah);
51 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
54 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
57 | (ah->ah_version == AR5K_AR5210 ?
66 if (ah->ah_version == AR5K_AR5210)
69 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
76 if (ah->ah_version == AR5K_AR5210)
79 AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
84 | (ah->ah_version == AR5K_AR5210 ?
88 | (ah->ah_version == AR5K_AR5210 ?
101 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
102 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
107 if (ah->ah_version == AR5K_AR5210)
108 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
116 * @ah: The &struct ath5k_hw
124 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
126 struct ath5k_statistics *stats = &ah->ah_sc->stats;
129 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
130 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
131 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
132 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
133 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
139 * @ah: The &struct ath5k_hw
148 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
150 if (ah->ah_version != AR5K_AR5212)
155 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
157 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
169 * @ah: The &struct ath5k_hw
172 static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
174 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
178 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
179 ath5k_hw_htoclock(ah, timeout));
187 * @ah: The &struct ath5k_hw
190 static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
192 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
196 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
197 ath5k_hw_htoclock(ah, timeout));
205 * @ah: The &struct ath5k_hw
208 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
210 return usec * ath5k_hw_get_clockrate(ah);
217 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
219 return clock / ath5k_hw_get_clockrate(ah);
225 * @ah: The &struct ath5k_hw
227 unsigned int ath5k_hw_get_clockrate(struct ath5k_hw *ah)
229 struct ieee80211_channel *channel = ah->ah_current_channel;
249 * @ah: The &struct ath5k_hw
251 static unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
253 struct ieee80211_channel *channel = ah->ah_current_channel;
267 * @ah: The &struct ath5k_hw
269 static unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
271 struct ieee80211_channel *channel = ah->ah_current_channel;
285 * @ah: The &struct ath5k_hw
290 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
292 struct ath_common *common = ath5k_hw_common(ah);
299 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
304 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
305 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
313 * @ah: The &struct ath5k_hw
319 void ath5k_hw_set_associd(struct ath5k_hw *ah)
321 struct ath_common *common = ath5k_hw_common(ah);
327 if (ah->ah_version == AR5K_AR5212)
333 ath5k_hw_reg_write(ah,
336 ath5k_hw_reg_write(ah,
342 ath5k_hw_disable_pspoll(ah);
346 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
349 ath5k_hw_enable_pspoll(ah, NULL, 0);
352 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
354 struct ath_common *common = ath5k_hw_common(ah);
359 if (ah->ah_version == AR5K_AR5212)
370 * @ah: The &struct ath5k_hw
377 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
379 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
385 * @ah: The &struct ath5k_hw
391 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
393 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
399 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
401 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
402 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
408 * @ah: The &struct ath5k_hw
416 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
420 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
423 if (ah->ah_version == AR5K_AR5212) {
424 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
438 * @ah: The &struct ath5k_hw
445 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
450 if (ah->ah_version == AR5K_AR5212) {
460 if (ah->ah_version == AR5K_AR5210 &&
468 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
470 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
473 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
476 if (ah->ah_version == AR5K_AR5212)
477 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
491 * @ah: The &struct ath5k_hw
495 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
512 tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
514 tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
515 tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
529 * @ah: The &struct ath5k_hw
534 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64)
536 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32);
537 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32);
543 * @ah: The &struct ath5k_hw
547 void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
551 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;
559 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
560 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
566 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
573 switch (ah->ah_sc->opmode) {
580 if (ah->ah_version == AR5K_AR5210) {
588 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF);
591 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM);
604 timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1);
610 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP ||
611 ah->ah_sc->opmode == NL80211_IFTYPE_MESH_POINT)
612 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
614 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
615 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
616 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
617 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
621 ath5k_hw_reset_tsf(ah);
623 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
632 if (ah->ah_version == AR5K_AR5210)
633 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR);
635 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR);
640 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV);
652 int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
659 type = ath5k_hw_reg_read(ah, AR5K_KEYTABLE_TYPE(entry));
662 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
669 ath5k_hw_reg_write(ah, 0,
682 if (ah->ah_version >= AR5K_AR5211) {
683 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
687 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
718 int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
770 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
773 ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry));
780 if (ah->ah_combined_mic) {
794 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
797 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
799 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC0(micentry));
800 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC1(micentry));
803 ath5k_hw_reg_write(ah, le32_to_cpu(~key0),
805 ath5k_hw_reg_write(ah, le32_to_cpu(~key1),
809 return ath5k_hw_set_key_lladdr(ah, entry, mac);
812 int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac)
832 ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry));
833 ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry));
841 * @ah: The &struct ath5k_hw
846 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
849 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class;
850 int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time;
853 ath5k_hw_set_slot_time(ah, slot_time);
854 ath5k_hw_set_ack_timeout(ah, ack_timeout);
855 ath5k_hw_set_cts_timeout(ah, cts_timeout);
857 ah->ah_coverage_class = coverage_class;