Lines Matching defs:ah
34 static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
41 if (ah->ah_version == AR5K_AR5210) {
42 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
43 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
45 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
46 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
51 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
55 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
96 ath5k_eeprom_init_header(struct ath5k_hw *ah)
98 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
113 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
128 ATH5K_ERR(ah->ah_sc, "Invalid max custom EEPROM size: "
142 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM "
150 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
153 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
169 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
181 if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && val)
201 static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
204 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
236 ah->ah_ant_ctl[mode][AR5K_ANT_CTL] =
238 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] =
244 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] =
261 static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
264 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
297 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
312 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
321 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
325 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
338 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
349 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6)
354 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
360 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_0)
368 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1)
393 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
419 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
426 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
480 ath5k_eeprom_init_modes(struct ath5k_hw *ah)
482 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
491 mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
492 mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
493 mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
501 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
505 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
511 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) {
523 ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max,
526 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
562 ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset)
564 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
571 ath5k_eeprom_read_freq_list(ah, &offset,
575 mask = AR5K_EEPROM_FREQ_M(ah->ah_ee_version);
615 ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
617 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
631 ath5k_eeprom_read_freq_list(ah, &offset,
659 ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
668 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_2)
680 ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode,
683 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
755 ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
757 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
769 ret = ath5k_eeprom_init_11a_pcal_freq(ah,
838 ath5k_get_pcdac_intercepts(ah, cdata->pcdac_min,
842 return ath5k_eeprom_convert_pcal_info_5111(ah, mode, pcal);
864 ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode,
867 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
975 ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode)
977 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1008 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
1084 return ath5k_eeprom_convert_pcal_info_5112(ah, mode, gen_chan_info);
1154 ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode,
1157 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1235 ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode)
1237 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1268 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
1276 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1284 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1414 return ath5k_eeprom_convert_pcal_info_2413(ah, mode, chinfo);
1426 ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
1428 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1520 ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah)
1522 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1527 if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) &&
1530 else if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0) &&
1539 err = read_pcal(ah, mode);
1543 err = ath5k_eeprom_read_target_rate_pwr_info(ah, mode);
1552 ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode)
1554 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1599 ath5k_eeprom_detach(struct ath5k_hw *ah)
1604 ath5k_eeprom_free_pcal_info(ah, mode);
1609 ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
1611 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1716 ath5k_eeprom_read_spur_chans(struct ath5k_hw *ah)
1718 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1751 ath5k_eeprom_init(struct ath5k_hw *ah)
1755 err = ath5k_eeprom_init_header(ah);
1759 err = ath5k_eeprom_init_modes(ah);
1763 err = ath5k_eeprom_read_pcal_info(ah);
1767 err = ath5k_eeprom_read_ctl_info(ah);
1771 err = ath5k_eeprom_read_spur_chans(ah);
1781 int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
1788 ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
1793 ret = ath5k_hw_eeprom_read(ah, offset, &data);