Lines Matching defs:ah
47 * @ah: The &struct ath5k_hw
49 void ath5k_hw_start_rx_dma(struct ath5k_hw *ah)
51 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
52 ath5k_hw_reg_read(ah, AR5K_CR);
58 * @ah: The &struct ath5k_hw
60 int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
64 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);
70 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
80 * @ah: The &struct ath5k_hw
82 u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah)
84 return ath5k_hw_reg_read(ah, AR5K_RXDP);
87 void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
89 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
100 * @ah: The &struct ath5k_hw
112 int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
116 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
119 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
122 if (ah->ah_version == AR5K_AR5210) {
123 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
128 switch (ah->ah_txq[queue].tqi_type) {
134 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
139 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V |
146 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
147 ath5k_hw_reg_read(ah, AR5K_CR);
150 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))
154 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
163 * @ah: The &struct ath5k_hw
171 int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
176 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
179 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
182 if (ah->ah_version == AR5K_AR5210) {
183 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
188 switch (ah->ah_txq[queue].tqi_type) {
195 ath5k_hw_reg_write(ah, 0, AR5K_BSR);
202 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
203 ath5k_hw_reg_read(ah, AR5K_CR);
208 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);
212 pending = ath5k_hw_reg_read(ah,
220 if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) &&
223 ath5k_hw_reg_write(ah,
229 ath5k_hw_reg_write(ah,
231 AR5K_REG_SM(ath5k_hw_reg_read(ah,
237 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
242 AR5K_REG_DISABLE_BITS(ah, AR5K_QUIET_CTL1,
248 pending = ath5k_hw_reg_read(ah,
254 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211,
259 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
268 u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
272 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
278 if (ah->ah_version == AR5K_AR5210) {
279 switch (ah->ah_txq[queue].tqi_type) {
294 return ath5k_hw_reg_read(ah, tx_reg);
300 * @ah: The &struct ath5k_hw
310 int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
314 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
320 if (ah->ah_version == AR5K_AR5210) {
321 switch (ah->ah_txq[queue].tqi_type) {
338 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
345 ath5k_hw_reg_write(ah, phys_addr, tx_reg);
350 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
358 imr = ath5k_hw_set_imr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);
360 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
373 if (ah->ah_version == AR5K_AR5210)
374 ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL);
376 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
385 ath5k_hw_set_imr(ah, imr);
397 * @ah: The &struct ath5k_hw
402 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
404 return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0;
410 * @ah: The @struct ath5k_hw
423 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
431 if (ah->ah_version == AR5K_AR5210) {
432 data = ath5k_hw_reg_read(ah, AR5K_ISR);
444 data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR);
454 *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr;
456 if (ah->ah_version != AR5K_AR5210) {
457 u32 sisr2 = ath5k_hw_reg_read(ah, AR5K_RAC_SISR2);
492 ah->ah_txq_isr |= AR5K_REG_MS(
493 ath5k_hw_reg_read(ah, AR5K_RAC_SISR3),
498 ah->ah_txq_isr |= AR5K_REG_MS(
499 ath5k_hw_reg_read(ah, AR5K_RAC_SISR3),
504 ah->ah_txq_isr |= AR5K_REG_MS(
505 ath5k_hw_reg_read(ah, AR5K_RAC_SISR4),
510 ah->ah_txq_isr |= AR5K_REG_MS(
511 ath5k_hw_reg_read(ah, AR5K_RAC_SISR0),
515 ah->ah_txq_isr |= AR5K_REG_MS(
516 ath5k_hw_reg_read(ah, AR5K_RAC_SISR0),
520 ah->ah_txq_isr |= AR5K_REG_MS(
521 ath5k_hw_reg_read(ah, AR5K_RAC_SISR1),
525 ah->ah_txq_isr |= AR5K_REG_MS(
526 ath5k_hw_reg_read(ah, AR5K_RAC_SISR1),
530 ah->ah_txq_isr |= AR5K_REG_MS(
531 ath5k_hw_reg_read(ah, AR5K_RAC_SISR2),
545 ATH5K_PRINTF("ISR: 0x%08x IMR: 0x%08x\n", data, ah->ah_imr);
553 * @ah: The &struct ath5k_hw
560 enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
564 old_mask = ah->ah_imr;
572 ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER);
573 ath5k_hw_reg_read(ah, AR5K_IER);
582 if (ah->ah_version != AR5K_AR5210) {
584 u32 simr2 = ath5k_hw_reg_read(ah, AR5K_SIMR2)
616 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
617 ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2);
624 ath5k_hw_reg_write(ah, int_mask, AR5K_IMR);
630 ath5k_hw_reg_write(ah, 0, AR5K_RXNOFRM);
633 ah->ah_imr = new_mask;
637 ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER);
638 ath5k_hw_reg_read(ah, AR5K_IER);