Lines Matching refs:tx_ctl
45 struct ath5k_hw_2w_tx_ctl *tx_ctl;
48 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
80 tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
91 tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
99 tx_ctl->tx_control_0 |=
115 tx_ctl->tx_control_0 |=
120 tx_ctl->tx_control_0 |=
124 tx_ctl->tx_control_1 |=
130 tx_ctl->tx_control_##_c |= \
135 tx_ctl->tx_control_##_c |= \
154 tx_ctl->tx_control_0 |=
156 tx_ctl->tx_control_1 |=
166 tx_ctl->tx_control_1 |= rtscts_duration &
184 struct ath5k_hw_4w_tx_ctl *tx_ctl;
187 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
223 tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
234 tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
236 tx_ctl->tx_control_0 |=
239 tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
241 tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0,
243 tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
247 tx_ctl->tx_control_##_c |= \
264 tx_ctl->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
265 tx_ctl->tx_control_1 |= AR5K_REG_SM(key_index,
276 tx_ctl->tx_control_2 |= rtscts_duration &
278 tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
293 struct ath5k_hw_4w_tx_ctl *tx_ctl;
314 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
318 tx_ctl->tx_control_2 |= \
321 tx_ctl->tx_control_3 |= \
344 struct ath5k_hw_2w_tx_ctl *tx_ctl;
347 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
370 ts->ts_rate[0] = AR5K_REG_MS(tx_ctl->tx_control_0,
396 struct ath5k_hw_4w_tx_ctl *tx_ctl;
399 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
434 ts->ts_rate[3] = AR5K_REG_MS(tx_ctl->tx_control_3,
437 ts->ts_retry[2] = AR5K_REG_MS(tx_ctl->tx_control_2,
442 ts->ts_rate[2] = AR5K_REG_MS(tx_ctl->tx_control_3,
445 ts->ts_retry[1] = AR5K_REG_MS(tx_ctl->tx_control_2,
450 ts->ts_rate[1] = AR5K_REG_MS(tx_ctl->tx_control_3,
453 ts->ts_retry[0] = AR5K_REG_MS(tx_ctl->tx_control_2,
458 ts->ts_rate[0] = tx_ctl->tx_control_3 &