Lines Matching defs:ah
33 * @ah: The &struct ath5k_hw
35 static int ath5k_hw_post(struct ath5k_hw *ah)
54 init_val = ath5k_hw_reg_read(ah, cur_reg);
58 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
59 cur_val = ath5k_hw_reg_read(ah, cur_reg);
62 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
68 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
73 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
74 cur_val = ath5k_hw_reg_read(ah, cur_reg);
77 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
83 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
87 ath5k_hw_reg_write(ah, init_val, cur_reg);
107 struct ath5k_hw *ah = sc->ah;
108 struct ath_common *common = ath5k_hw_common(ah);
117 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
118 ah->ah_turbo = false;
119 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
120 ah->ah_imr = 0;
121 ah->ah_atim_window = 0;
122 ah->ah_aifs = AR5K_TUNE_AIFS;
123 ah->ah_cw_min = AR5K_TUNE_CWMIN;
124 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
125 ah->ah_software_retry = false;
126 ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
127 ah->ah_noise_floor = -95; /* until first NF calibration is run */
129 ah->ah_current_channel = &sc->channels[0];
134 srev = ath5k_hw_reg_read(ah, AR5K_SREV);
136 ah->ah_version = AR5K_AR5210;
138 ah->ah_version = AR5K_AR5211;
140 ah->ah_version = AR5K_AR5212;
143 ret = ath5k_hw_init_desc_functions(ah);
148 ret = ath5k_hw_nic_wakeup(ah, 0, true);
153 ah->ah_mac_srev = srev;
154 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
155 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
157 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
159 ah->ah_phy = AR5K_PHY(0);
162 switch (ah->ah_radio_5ghz_revision & 0xf0) {
164 ah->ah_radio = AR5K_RF5111;
165 ah->ah_single_chip = false;
166 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
171 ah->ah_radio = AR5K_RF5112;
172 ah->ah_single_chip = false;
173 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
177 ah->ah_radio = AR5K_RF2413;
178 ah->ah_single_chip = true;
181 ah->ah_radio = AR5K_RF5413;
182 ah->ah_single_chip = true;
185 ah->ah_radio = AR5K_RF2316;
186 ah->ah_single_chip = true;
189 ah->ah_radio = AR5K_RF2317;
190 ah->ah_single_chip = true;
193 if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
194 ah->ah_mac_version == AR5K_SREV_AR2417){
195 ah->ah_radio = AR5K_RF2425;
196 ah->ah_single_chip = true;
198 ah->ah_radio = AR5K_RF5413;
199 ah->ah_single_chip = true;
204 if (ah->ah_version == AR5K_AR5210) {
205 ah->ah_radio = AR5K_RF5110;
206 ah->ah_single_chip = false;
207 } else if (ah->ah_version == AR5K_AR5211) {
208 ah->ah_radio = AR5K_RF5111;
209 ah->ah_single_chip = false;
210 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
212 } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
213 ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
214 ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
215 ah->ah_radio = AR5K_RF2425;
216 ah->ah_single_chip = true;
217 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
219 ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
220 ah->ah_radio = AR5K_RF5112;
221 ah->ah_single_chip = false;
222 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
223 } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
224 ah->ah_radio = AR5K_RF2316;
225 ah->ah_single_chip = true;
226 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
227 } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
228 ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
229 ah->ah_radio = AR5K_RF5413;
230 ah->ah_single_chip = true;
231 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
232 } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
233 ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
234 ah->ah_radio = AR5K_RF2413;
235 ah->ah_single_chip = true;
236 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
256 ret = ath5k_hw_post(ah);
262 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);
268 ret = ath5k_eeprom_init(ah);
274 ee = &ah->ah_capabilities.cap_eeprom;
279 if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
280 ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
281 ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
284 ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
285 ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
291 ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
293 ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);
296 ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
299 ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
300 ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
301 ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
304 ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
309 ret = ath5k_hw_set_capabilities(ah);
317 ah->ah_aes_support = srev >= AR5K_SREV_AR5212_V4 &&
322 ah->ah_combined_mic = true;
323 AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
328 ath5k_hw_set_lladdr(ah, (u8[ETH_ALEN]){});
332 ath5k_hw_set_associd(ah);
333 ath5k_hw_set_opmode(ah, sc->opmode);
335 ath5k_hw_rfgain_opt_init(ah);
337 ath5k_hw_init_nfcal_hist(ah);
340 ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);
344 kfree(ah);
351 * @ah: The &struct ath5k_hw
353 void ath5k_hw_detach(struct ath5k_hw *ah)
355 __set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
357 if (ah->ah_rf_banks != NULL)
358 kfree(ah->ah_rf_banks);
360 ath5k_eeprom_detach(ah);