Lines Matching defs:ah
57 ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level)
70 ATH5K_ERR(ah->ah_sc, "noise immuniy level %d out of range",
75 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
77 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_AGCCOARSE,
79 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_AGCCOARSE,
81 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG,
84 ah->ah_sc->ani_state.noise_imm_level = level;
85 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level);
96 ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
101 level > ah->ah_sc->ani_state.max_spur_level) {
102 ATH5K_ERR(ah->ah_sc, "spur immunity level %d out of range",
107 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
110 ah->ah_sc->ani_state.spur_level = level;
111 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level);
121 ath5k_ani_set_firstep_level(struct ath5k_hw *ah, int level)
126 ATH5K_ERR(ah->ah_sc, "firstep level %d out of range", level);
130 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG,
133 ah->ah_sc->ani_state.firstep_level = level;
134 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level);
145 ath5k_ani_set_ofdm_weak_signal_detection(struct ath5k_hw *ah, bool on)
154 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
156 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
158 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_HIGH_THR,
160 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_HIGH_THR,
162 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_HIGH_THR,
164 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
168 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
171 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
174 ah->ah_sc->ani_state.ofdm_weak_sig = on;
175 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "turned %s",
186 ath5k_ani_set_cck_weak_signal_detection(struct ath5k_hw *ah, bool on)
189 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_CCK_CROSSCORR,
191 ah->ah_sc->ani_state.cck_weak_sig = on;
192 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "turned %s",
209 ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
212 int rssi = ah->ah_beacon_rssi_avg.avg;
214 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "raise immunity (%s)",
219 ath5k_ani_set_noise_immunity_level(ah, as->noise_imm_level + 1);
225 as->spur_level < ah->ah_sc->ani_state.max_spur_level) {
226 ath5k_ani_set_spur_immunity_level(ah, as->spur_level + 1);
231 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP) {
233 ath5k_ani_set_firstep_level(ah, as->firstep_level + 1);
244 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI,
249 ath5k_ani_set_ofdm_weak_signal_detection(ah, false);
250 ath5k_ani_set_spur_immunity_level(ah, 0);
255 ath5k_ani_set_firstep_level(ah, as->firstep_level + 1);
261 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI,
264 ath5k_ani_set_ofdm_weak_signal_detection(ah, true);
266 ath5k_ani_set_firstep_level(ah, as->firstep_level + 1);
268 } else if (ah->ah_current_channel->band == IEEE80211_BAND_2GHZ) {
271 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI,
274 ath5k_ani_set_ofdm_weak_signal_detection(ah, false);
276 ath5k_ani_set_firstep_level(ah, 0);
282 ath5k_ani_set_cck_weak_signal_detection(ah, false);
295 ath5k_ani_lower_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as)
297 int rssi = ah->ah_beacon_rssi_avg.avg;
299 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "lower immunity");
301 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP) {
304 ath5k_ani_set_firstep_level(ah, as->firstep_level - 1);
317 ath5k_ani_set_ofdm_weak_signal_detection(ah,
322 ath5k_ani_set_firstep_level(ah,
329 ath5k_ani_set_firstep_level(ah,
338 ath5k_ani_set_spur_immunity_level(ah, as->spur_level - 1);
344 ath5k_ani_set_noise_immunity_level(ah, as->noise_imm_level - 1);
362 ath5k_hw_ani_get_listen_time(struct ath5k_hw *ah, struct ath5k_ani_state *as)
367 ath5k_hw_reg_write(ah, AR5K_MIBC_FMC, AR5K_MIBC);
369 as->pfc_cycles = ath5k_hw_reg_read(ah, AR5K_PROFCNT_CYCLE);
370 as->pfc_busy = ath5k_hw_reg_read(ah, AR5K_PROFCNT_RXCLR);
371 as->pfc_tx = ath5k_hw_reg_read(ah, AR5K_PROFCNT_TX);
372 as->pfc_rx = ath5k_hw_reg_read(ah, AR5K_PROFCNT_RX);
374 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX);
375 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX);
376 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR);
377 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE);
379 ath5k_hw_reg_write(ah, 0, AR5K_MIBC);
402 ath5k_ani_save_and_clear_phy_errors(struct ath5k_hw *ah,
407 if (!ah->ah_capabilities.cap_has_phyerr_counters)
410 ofdm_err = ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1);
411 cck_err = ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2);
414 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_OFDM_TRIG_HIGH,
416 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_CCK_TRIG_HIGH,
446 ath5k_ani_period_restart(struct ath5k_hw *ah, struct ath5k_ani_state *as)
471 ath5k_ani_calibration(struct ath5k_hw *ah)
473 struct ath5k_ani_state *as = &ah->ah_sc->ani_state;
479 listen = ath5k_hw_ani_get_listen_time(ah, as);
485 ath5k_ani_save_and_clear_phy_errors(ah, as);
492 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI,
494 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI,
501 ath5k_ani_raise_immunity(ah, as, ofdm_flag);
502 ath5k_ani_period_restart(ah, as);
507 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI,
512 ath5k_ani_lower_immunity(ah, as);
514 ath5k_ani_period_restart(ah, as);
532 ath5k_ani_mib_intr(struct ath5k_hw *ah)
534 struct ath5k_ani_state *as = &ah->ah_sc->ani_state;
538 if (!ah->ah_capabilities.cap_has_phyerr_counters)
542 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT);
543 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT);
545 if (ah->ah_sc->ani_state.ani_mode != ATH5K_ANI_MODE_AUTO)
551 if (ath5k_ani_save_and_clear_phy_errors(ah, as) == 0)
556 tasklet_schedule(&ah->ah_sc->ani_tasklet);
567 ath5k_ani_phy_error_report(struct ath5k_hw *ah,
570 struct ath5k_ani_state *as = &ah->ah_sc->ani_state;
575 tasklet_schedule(&ah->ah_sc->ani_tasklet);
579 tasklet_schedule(&ah->ah_sc->ani_tasklet);
592 ath5k_enable_phy_err_counters(struct ath5k_hw *ah)
594 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_OFDM_TRIG_HIGH,
596 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_CCK_TRIG_HIGH,
598 ath5k_hw_reg_write(ah, AR5K_PHY_ERR_FIL_OFDM, AR5K_PHYERR_CNT1_MASK);
599 ath5k_hw_reg_write(ah, AR5K_PHY_ERR_FIL_CCK, AR5K_PHYERR_CNT2_MASK);
602 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT);
603 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT);
613 ath5k_disable_phy_err_counters(struct ath5k_hw *ah)
615 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT1);
616 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT2);
617 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT1_MASK);
618 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT2_MASK);
621 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT);
622 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT);
633 ath5k_ani_init(struct ath5k_hw *ah, enum ath5k_ani_mode mode)
636 if (ah->ah_version < AR5K_AR5212)
640 memset(&ah->ah_sc->ani_state, 0, sizeof(ah->ah_sc->ani_state));
643 if (ah->ah_mac_srev < AR5K_SREV_AR2414)
644 ah->ah_sc->ani_state.max_spur_level = 7;
646 ah->ah_sc->ani_state.max_spur_level = 2;
650 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "ANI off\n");
652 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI,
654 ath5k_ani_set_noise_immunity_level(ah, 0);
655 ath5k_ani_set_spur_immunity_level(ah, 0);
656 ath5k_ani_set_firstep_level(ah, 0);
657 ath5k_ani_set_ofdm_weak_signal_detection(ah, true);
658 ath5k_ani_set_cck_weak_signal_detection(ah, true);
660 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI,
662 ath5k_ani_set_noise_immunity_level(ah,
664 ath5k_ani_set_spur_immunity_level(ah,
665 ah->ah_sc->ani_state.max_spur_level);
666 ath5k_ani_set_firstep_level(ah, ATH5K_ANI_MAX_FIRSTEP_LVL);
667 ath5k_ani_set_ofdm_weak_signal_detection(ah, false);
668 ath5k_ani_set_cck_weak_signal_detection(ah, false);
670 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "ANI auto\n");
671 ath5k_ani_set_noise_immunity_level(ah, 0);
672 ath5k_ani_set_spur_immunity_level(ah, 0);
673 ath5k_ani_set_firstep_level(ah, 0);
674 ath5k_ani_set_ofdm_weak_signal_detection(ah, true);
675 ath5k_ani_set_cck_weak_signal_detection(ah, false);
683 if (ah->ah_capabilities.cap_has_phyerr_counters)
684 ath5k_enable_phy_err_counters(ah);
686 ath5k_hw_set_rx_filter(ah, ath5k_hw_get_rx_filter(ah) |
689 if (ah->ah_capabilities.cap_has_phyerr_counters)
690 ath5k_disable_phy_err_counters(ah);
692 ath5k_hw_set_rx_filter(ah, ath5k_hw_get_rx_filter(ah) &
696 ah->ah_sc->ani_state.ani_mode = mode;
705 ath5k_ani_print_counters(struct ath5k_hw *ah)
709 ath5k_hw_reg_read(ah, AR5K_ACK_FAIL));
711 ath5k_hw_reg_read(ah, AR5K_RTS_FAIL));
713 ath5k_hw_reg_read(ah, AR5K_RTS_OK));
715 ath5k_hw_reg_read(ah, AR5K_FCS_FAIL));
719 ath5k_hw_reg_read(ah, AR5K_PROFCNT_TX));
721 ath5k_hw_reg_read(ah, AR5K_PROFCNT_RX));
723 ath5k_hw_reg_read(ah, AR5K_PROFCNT_RXCLR));
725 ath5k_hw_reg_read(ah, AR5K_PROFCNT_CYCLE));
728 ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1));
730 ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2));
732 ath5k_hw_reg_read(ah, AR5K_OFDM_FIL_CNT));
734 ath5k_hw_reg_read(ah, AR5K_CCK_FIL_CNT));