Lines Matching refs:d0
198 movel OR1, %d0
199 andl #0xF00007FF, %d0 // mask AMxx bits
200 orl #0xFFFF800 & ~(MAX_RAM_SIZE - 1), %d0 // update RAM bank size
201 movel %d0, OR1
205 clrl %d0 // D0 = 4 * port
206 init_1: tstl ch_status_addr(%d0)
208 addl #VALUE_WINDOW, ch_status_addr(%d0)
209 init_2: addl #4, %d0
210 cmpl #4 * 4, %d0
259 main_1: clrl %d0 // D0 = 4 * port
282 addl #4, %d0 // D0 = 4 * next port
283 cmpl #4 * 4, %d0
292 movel ch_status_addr(%d0), %a0 // A0 = port status address
297 clrl tx_in(%d0)
298 clrl tx_out(%d0)
299 clrl tx_count(%d0)
300 clrl rx_in(%d0)
303 andl clocking_mask(%d0), %d1
306 orl clocking_txfromrx(%d0), %d1
310 orl clocking_ext(%d0), %d1
314 orw #STATUS_CABLE_DTR, csr_output(%d0) // DTR on
318 movel first_buffer(%d0), %d1 // D1 = starting buffer address
319 movel tx_first_bd(%d0), %a1 // A1 = starting TX BD address
347 movel scc_base_addr(%d0), %a1 // A1 = SCC_BASE address
348 movel scc_reg_addr(%d0), %a2 // A2 = SCC_REGS address
353 movel tx_first_bd(%d0), %d1
367 movew #2, parity_bytes(%d0)
377 movew #4, parity_bytes(%d0)
387 movew #2, parity_bytes(%d0)
397 movew #4, parity_bytes(%d0)
405 clrw parity_bytes(%d0)
418 movel %d0, %d1
434 movel scc_reg_addr(%d0), %a0 // A0 = SCC_REGS address
438 andw #~STATUS_CABLE_DTR, csr_output(%d0) // DTR off
441 movel ch_status_addr(%d0), %d1
449 cmpl #TX_BUFFERS, tx_count(%d0)
452 movel tx_out(%d0), %d1
455 addl ch_status_addr(%d0), %d2
463 addl tx_first_bd(%d0), %d1 // D1 = current tx_out BD addr
472 movel tx_out(%d0), %d1
477 tx_1: movel %d1, tx_out(%d0)
479 addl #1, tx_count(%d0)
488 rx: movel rx_in(%d0), %d1 // D1 = rx_in BD#
490 addl rx_first_bd(%d0), %d1 // D1 = current rx_in BD address
498 tstw parity_bytes(%d0)
507 subw parity_bytes(%d0), %d3 // D3 = packet length
525 movel packet_full(%d0), (%d2) // update desc stat
540 movel rx_in(%d0), %d1
545 rx_2: movel %d1, rx_in(%d0)
549 movel ch_status_addr(%d0), %d2
554 movel ch_status_addr(%d0), %d2
564 tx_end: tstl tx_count(%d0)
567 movel tx_in(%d0), %d1
570 addl tx_first_bd(%d0), %d1 // D1 = current tx_in BD address
576 orl bell_tx(%d0), %d6 // signal host that TX desc freed
577 subl #1, tx_count(%d0)
578 movel tx_in(%d0), %d1
584 movel %d1, tx_in(%d0)
588 addl ch_status_addr(%d0), %d2
607 movel %d0, -(%sp)
610 movel PLX_DMA_CMD_STS, %d0 // do not btst PLX register directly
611 btstl #4, %d0 // transfer done?
618 movel %d0, -(%sp)
621 movel PLX_DMA_CMD_STS, %d0 // do not btst PLX register directly
622 btstl #12, %d0 // transfer done?
630 movel (%sp)+, %d0
642 movel %d0, -(%sp)
644 movel PLX_DOORBELL_TO_CARD, %d0
645 movel %d0, PLX_DOORBELL_TO_CARD // confirm all requests
646 orl %d0, channel_stats
650 movel (%sp)+, %d0
686 movel %d0, -(%sp)
692 clrl %d0 // D0 = 4 * port
727 movew csr_output(%d0), %d2
733 cmpw old_csr_output(%d0), %d1
735 movew %d1, old_csr_output(%d0)
740 andw dcd_mask(%d0), %d1
751 movel ch_status_addr(%d0), %a1
755 movel bell_cable(%d0), PLX_DOORBELL_FROM_CARD // signal the host
759 addl #4, %d0 // D0 = 4 * next port
760 cmpl #4 * 4, %d0
767 movel (%sp)+, %d0
783 movel #128 * 1024, %d0 // D0 = RAM size tested
785 cmpl #MAX_RAM_SIZE, %d0
787 movel %d0, %a0
792 lsll #1, %d0
802 movel %d0, %a0 // A0 = fill ptr
803 subl #firmware_end + 4, %d0
804 lsrl #2, %d0
805 movel %d0, %d1 // D1 = DBf counter
815 dbnew %d0, ram_test_loop
817 subl #0x10000, %d0
818 cmpl #0xFFFFFFFF, %d0