Lines Matching refs:REGBASE
89 REGBASE = DPRBASE + 0x1000
90 PICR = REGBASE + 0x026 // 16-bit periodic irq control
91 PITR = REGBASE + 0x02A // 16-bit periodic irq timing
92 OR1 = REGBASE + 0x064 // 32-bit RAM bank #1 options
93 CICR = REGBASE + 0x540 // 32(24)-bit CP interrupt config
94 CIMR = REGBASE + 0x548 // 32-bit CP interrupt mask
95 CISR = REGBASE + 0x54C // 32-bit CP interrupts in-service
96 PADIR = REGBASE + 0x550 // 16-bit PortA data direction bitmap
97 PAPAR = REGBASE + 0x552 // 16-bit PortA pin assignment bitmap
98 PAODR = REGBASE + 0x554 // 16-bit PortA open drain bitmap
99 PADAT = REGBASE + 0x556 // 16-bit PortA data register
101 PCDIR = REGBASE + 0x560 // 16-bit PortC data direction bitmap
102 PCPAR = REGBASE + 0x562 // 16-bit PortC pin assignment bitmap
103 PCSO = REGBASE + 0x564 // 16-bit PortC special options
104 PCDAT = REGBASE + 0x566 // 16-bit PortC data register
105 PCINT = REGBASE + 0x568 // 16-bit PortC interrupt control
106 CR = REGBASE + 0x5C0 // 16-bit Command register
108 SCC1_REGS = REGBASE + 0x600
109 SCC2_REGS = REGBASE + 0x620
110 SCC3_REGS = REGBASE + 0x640
111 SCC4_REGS = REGBASE + 0x660
112 SICR = REGBASE + 0x6EC // 32-bit SI clock route