Lines Matching refs:x20
40 #define CMDR_XREP 0x20
51 #define MODE_MDS0 0x20
67 #define CCR1_CASSYM 0x20
68 #define CCR1_EDLX 0x20
79 #define CCR3_EPT 0x20
90 #define RTR1_TS2 0x20
99 #define RTR2_TS10 0x20
108 #define RTR3_TS18 0x20
117 #define RTR4_TS26 0x20
130 #define TTR1_TS2 0x20
139 #define TTR2_TS10 0x20
148 #define TTR3_TS18 0x20
157 #define TTR4_TS26 0x20
172 #define IMR0_T8MS 0x20
173 #define IMR0_ISF 0x20
184 #define IMR1_ALLS 0x20
193 #define IMR2_MFAR 0x20
203 #define IMR3_LMFA16 0x20
207 #define IMR3_XSLP 0x20
216 #define IMR4_CER 0x20
227 #define FMR0_RC1 0x20
239 #define FMR1_ENSA 0x20
242 #define FMR1_EDL 0x20
253 #define FMR2_RTM 0x20
254 #define FMR2_SSP 0x20
264 #define LOOP_ECLB 0x20
268 #define FMR3_XLD 0x20
274 #define FMR4_XRA 0x20
283 #define FMR5_XLD 0x20
292 #define LOOP_ECLB 0x20
307 #define XSW_XRA 0x20
321 #define XSP_TT0 0x20
334 #define XC0_SA6E 0x20
344 #define XC1_XTO5 0x20
356 #define RC0_CRCI 0x20
366 #define RC1_RTO5 0x20
380 #define XPM0_XP10 0x20
389 #define XPM1_XP23 0x20
398 #define XPM2_DAXLT 0x20
410 #define TSWM_TRA 0x20
423 #define IDLE_IDL5 0x20
436 #define XSA4_XS45 0x20
445 #define XSA5_XS55 0x20
454 #define XSA6_XS65 0x20
463 #define XSA7_XS75 0x20
472 #define XSA8_XS85 0x20
485 #define XDL1_XDL15 0x20
494 #define XDL2_XDL25 0x20
503 #define XDL3_XDL35 0x20
516 #define E1_ICB1_IC2 0x20
525 #define E1_ICB2_IC10 0x20
534 #define E1_ICB3_IC18 0x20
543 #define E1_ICB4_IC26 0x20
555 #define T1_ICB1_IC3 0x20
564 #define T1_ICB2_IC11 0x20
573 #define T1_ICB3_IC19 0x20
595 #define CCB1_CH3 0x20
604 #define CCB2_CH11 0x20
613 #define CCB3_CH19 0x20
626 #define LIM0_SCL1 0x20
635 #define LIM1_RIL1 0x20
648 #define PCDR_PCD5 0x20
657 #define PCRR_PCR5 0x20
669 #define LIM2_DJA2 0x20
681 #define SIC1_RBS1 0x20
690 #define DEC_DCEC3 0x20
708 #define FRS0_LFA 0x20
716 #define FRS1_TS16LOS 0x20
731 #define FRS2_ESC0 0x20
733 #define FRS3_FEH5 0x20
745 #define RSW_RRA 0x20
770 #define FECL_FE5 0x20
779 #define FECH_FE13 0x20
792 #define CVCL_CV5 0x20
801 #define CVCH_CV13 0x20
814 #define CEC1L_CR5 0x20
823 #define CEC1H_CR13 0x20
832 #define CEC2L_CR5 0x20
841 #define CEC2H_CR13 0x20
850 #define CEC3L_CR5 0x20
859 #define CEC3H_CR13 0x20
873 #define CECL_CR5 0x20
882 #define CECH_CR13 0x20
894 #define EBCL_EB5 0x20
903 #define EBCH_EB13 0x20
916 #define RSA4_RS45 0x20
925 #define RSA5_RS55 0x20
934 #define RSA6_RS65 0x20
943 #define RSA7_RS75 0x20
952 #define RSA8_RS85 0x20
962 #define RSA6S_SX 0x20
975 #define RDL1_RDL15 0x20
984 #define RDL2_RDL25 0x20
993 #define RDL3_RDL35 0x20
1007 #define SIS_XREP 0x20
1019 #define RSIS_CRC16 0x20
1033 #define RBCL_RBC5 0x20
1053 #define FISR0_T8MS 0x20
1054 #define FISR0_ISF 0x20
1066 #define FISR1_ALLS 0x20
1074 #define FISR2_MFAR 0x20
1084 #define FISR3_LMFA16 0x20
1088 #define FISR3_XSLP 0x20
1158 #define XC0 0x20 /* Transmit Control 0 */