Lines Matching refs:x80
96 /* DMA channel 0 (port 0 RX) registers - offset 0x80
102 #define DMAC0RX_OFFSET 0x80
161 #define ST_TX_EOM 0x80 /* End of frame */
164 #define ST_RX_EOM 0x80 /* End of frame */
173 #define DIR_EOTE 0x80 /* Transfer completed */
179 #define DSR_EOT 0x80 /* Transfer completed */
187 #define DMER_DME 0x80 /* DMA Master Enable */
194 #define MD0_HDLC 0x80 /* Bit-sync HDLC mode */
207 #define MD2_MANCHESTER 0x80
219 #define ST1_UDRN 0x80 /* MSCI TX underrun */
225 #define IE0_TXINT 0x80 /* TX INT MSCI interrupt enable */
227 #define IE1_UDRN 0x80 /* TX underrun MSCI interrupt enable */