Lines Matching refs:CCR0
266 #define CCR0 0x08
820 scc_writel(0x00000000, dpriv, dev, CCR0);
1030 scc_patchl(0, PowerUp, dpriv, dev, CCR0);
1040 scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
1093 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1149 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1213 * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00).
1292 state = scc_readl(dpriv, CCR0);
1306 scc_writel(state, dpriv, dev, CCR0);
1327 scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);