Lines Matching defs:dpriv
184 #define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
388 static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv,
394 state = dpriv->scc_regs[offset >> 2];
397 dpriv->scc_regs[offset >> 2] = state;
398 writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
401 static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,
408 dpriv->scc_regs[offset >> 2] = bits;
409 writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
412 static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset)
414 return dpriv->scc_regs[offset >> 2];
417 static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev)
420 readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
421 return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
424 static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv,
427 dpriv->ltda = dpriv->tx_fd_dma +
428 ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD);
429 writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
431 readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
434 static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv,
437 dpriv->lrda = dpriv->rx_fd_dma +
438 ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD);
439 writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
442 static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv)
444 return dpriv->tx_current == dpriv->tx_dirty;
447 static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv,
450 return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda;
453 static int state_check(u32 state, struct dscc4_dev_priv *dpriv,
459 if (SOURCE_ID(state) != dpriv->dev_id) {
474 struct dscc4_dev_priv *dpriv,
478 dev->name, dpriv->tx_current, dpriv->tx_dirty, msg);
481 static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
483 struct pci_dev *pdev = dpriv->pci_priv->pdev;
484 struct TxFD *tx_fd = dpriv->tx_fd;
485 struct RxFD *rx_fd = dpriv->rx_fd;
489 pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma);
490 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
492 skbuff = dpriv->tx_skbuff;
503 skbuff = dpriv->rx_skbuff;
515 static inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv,
518 unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE;
519 struct RxFD *rx_fd = dpriv->rx_fd + dirty;
525 dpriv->rx_skbuff[dirty] = skb;
528 rx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
540 static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv,
546 if (!(scc_readl_star(dpriv, dev) & SccBusy)) {
586 static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
588 int cur = dpriv->iqtx_current%IRQ_RING_SIZE;
592 if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
593 (dpriv->iqtx[cur] & cpu_to_le32(Xpr)))
605 static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
608 struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
609 struct pci_dev *pdev = dpriv->pci_priv->pdev;
613 skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE];
640 while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) {
641 if (try_get_rx_skb(dpriv, dev) < 0)
643 dpriv->rx_dirty++;
645 dscc4_rx_update(dpriv, dev);
674 struct dscc4_dev_priv *dpriv;
752 dpriv = priv->root + i;
753 dpriv->iqtx = (__le32 *) pci_alloc_consistent(pdev,
754 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma);
755 if (!dpriv->iqtx)
757 writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4);
760 dpriv = priv->root + i;
761 dpriv->iqrx = (__le32 *) pci_alloc_consistent(pdev,
762 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma);
763 if (!dpriv->iqrx)
765 writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4);
784 dpriv = priv->root + i;
786 dpriv->iqrx, dpriv->iqrx_dma);
791 dpriv = priv->root + i;
793 dpriv->iqtx, dpriv->iqtx_dma);
816 static void dscc4_init_registers(struct dscc4_dev_priv *dpriv,
820 scc_writel(0x00000000, dpriv, dev, CCR0);
822 scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);
824 scc_writel(0x02408000, dpriv, dev, CCR1);
827 scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);
829 //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2);
832 static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz)
839 dpriv->pci_priv->xtal_hz = hz;
881 struct dscc4_dev_priv *dpriv = root + i;
882 struct net_device *d = dscc4_to_dev(dpriv);
891 dpriv->dev_id = i;
892 dpriv->pci_priv = ppriv;
893 dpriv->base_addr = ioaddr;
894 spin_lock_init(&dpriv->lock);
899 dscc4_init_registers(dpriv, d);
900 dpriv->parity = PARITY_CRC16_PR0_CCITT;
901 dpriv->encoding = ENCODING_NRZ;
910 dscc4_release_ring(dpriv);
940 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
945 dpriv->timer.expires = jiffies + TX_TIMEOUT;
946 add_timer(&dpriv->timer);
953 static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv)
955 sync_serial_settings *settings = &dpriv->settings;
958 struct net_device *dev = dscc4_to_dev(dpriv);
1007 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1011 if ((dscc4_loopback_check(dpriv) < 0))
1017 ppriv = dpriv->pci_priv;
1028 if (dpriv->flags & FakeReset) {
1029 dpriv->flags &= ~FakeReset;
1030 scc_patchl(0, PowerUp, dpriv, dev, CCR0);
1031 scc_patchl(0, 0x00050000, dpriv, dev, CCR2);
1032 scc_writel(EventsMask, dpriv, dev, IMR);
1038 dpriv->flags = NeedIDR | NeedIDT;
1040 scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
1049 if (scc_readl_star(dpriv, dev) & SccBusy) {
1056 scc_writel(EventsMask, dpriv, dev, IMR);
1059 scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);
1061 if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0)
1071 if ((ret = dscc4_xpr_ack(dpriv)) < 0) {
1077 dscc4_tx_print(dev, dpriv, "Open");
1082 init_timer(&dpriv->timer);
1083 dpriv->timer.expires = jiffies + 10*HZ;
1084 dpriv->timer.data = (unsigned long)dev;
1085 dpriv->timer.function = dscc4_timer;
1086 add_timer(&dpriv->timer);
1092 scc_writel(0xffffffff, dpriv, dev, IMR);
1093 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1101 static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1109 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1110 struct dscc4_pci_priv *ppriv = dpriv->pci_priv;
1114 next = dpriv->tx_current%TX_RING_SIZE;
1115 dpriv->tx_skbuff[next] = skb;
1116 tx_fd = dpriv->tx_fd + next;
1125 spin_lock(&dpriv->lock);
1126 while (dscc4_tx_poll(dpriv, dev));
1127 spin_unlock(&dpriv->lock);
1131 dscc4_tx_print(dev, dpriv, "Xmit");
1133 if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE))
1136 if (dscc4_tx_quiescent(dpriv, dev))
1137 dscc4_do_tx(dpriv, dev);
1144 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1146 del_timer_sync(&dpriv->timer);
1149 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1150 scc_patchl(0x00050000, 0, dpriv, dev, CCR2);
1151 scc_writel(0xffffffff, dpriv, dev, IMR);
1153 dpriv->flags |= FakeReset;
1173 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1182 xtal = dpriv->pci_priv->xtal_hz;
1185 if (dscc4_check_clock_ability(dpriv->dev_id) < 0)
1218 scc_writel(brr, dpriv, dev, BRR);
1227 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1228 const size_t size = sizeof(dpriv->settings);
1244 if (copy_to_user(line, &dpriv->settings, size))
1252 if (dpriv->flags & FakeReset) {
1257 if (copy_from_user(&dpriv->settings, line, size))
1259 ret = dscc4_set_iface(dpriv, dev);
1284 static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv,
1287 sync_serial_settings *settings = &dpriv->settings;
1292 state = scc_readl(dpriv, CCR0);
1306 scc_writel(state, dpriv, dev, CCR0);
1312 static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
1325 i = dscc4_match(encoding, dpriv->encoding);
1327 scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);
1333 static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
1336 sync_serial_settings *settings = &dpriv->settings;
1339 state = scc_readl(dpriv, CCR1);
1347 scc_writel(state, dpriv, dev, CCR1);
1351 static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
1362 i = dscc4_match(crc, dpriv->parity);
1364 scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
1370 static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1384 if ((ret = p->action(dpriv, dev)) < 0)
1450 struct dscc4_dev_priv *dpriv)
1452 struct net_device *dev = dscc4_to_dev(dpriv);
1457 cur = dpriv->iqtx_current%IRQ_RING_SIZE;
1458 state = le32_to_cpu(dpriv->iqtx[cur]);
1466 if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)
1469 if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) &&
1470 !dscc4_tx_done(dpriv))
1471 dscc4_do_tx(dpriv, dev);
1475 dpriv->iqtx[cur] = 0;
1476 dpriv->iqtx_current++;
1478 if (state_check(state, dpriv, dev, "Tx") < 0)
1487 dscc4_tx_print(dev, dpriv, "Alls");
1492 cur = dpriv->tx_dirty%TX_RING_SIZE;
1493 tx_fd = dpriv->tx_fd + cur;
1494 skb = dpriv->tx_skbuff[cur];
1503 dpriv->tx_skbuff[cur] = NULL;
1504 ++dpriv->tx_dirty;
1528 dpriv->flags = NeedIDT;
1531 dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
1532 writel(Action, dpriv->base_addr + GCMDR);
1555 if (!(scc_readl_star(dpriv, dev) & SccBusy))
1561 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1563 if (dpriv->flags & NeedIDT) {
1565 dscc4_tx_print(dev, dpriv, "Xpr");
1566 ring = dpriv->tx_fd_dma +
1567 (dpriv->tx_dirty%TX_RING_SIZE)*
1570 dscc4_do_tx(dpriv, dev);
1574 dpriv->flags &= ~NeedIDT;
1576 if (dpriv->flags & NeedIDR) {
1577 ring = dpriv->rx_fd_dma +
1578 (dpriv->rx_current%RX_RING_SIZE)*
1581 dscc4_rx_update(dpriv, dev);
1585 dpriv->flags &= ~NeedIDR;
1588 scc_writel(0x08050008, dpriv, dev, CCR2);
1603 while (!dscc4_tx_poll(dpriv, dev));
1618 struct dscc4_dev_priv *dpriv)
1620 struct net_device *dev = dscc4_to_dev(dpriv);
1625 cur = dpriv->iqrx_current%IRQ_RING_SIZE;
1626 state = le32_to_cpu(dpriv->iqrx[cur]);
1629 dpriv->iqrx[cur] = 0;
1630 dpriv->iqrx_current++;
1632 if (state_check(state, dpriv, dev, "Rx") < 0)
1644 cur = dpriv->rx_current%RX_RING_SIZE;
1645 rx_fd = dpriv->rx_fd + cur;
1657 //while (dpriv->rx_needs_refill) {
1662 rx_fd = dpriv->rx_fd;
1664 //dpriv->rx_needs_refill--;
1665 try_get_rx_skb(dpriv, dev);
1675 dscc4_rx_skb(dpriv, dev);
1719 // dscc4_rx_dump(dpriv);
1720 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1722 scc_patchl(RxActivate, 0, dpriv, dev, CCR2);
1728 scc_writel(RxSccRes, dpriv, dev, CMDR);
1729 dpriv->flags |= RdoSet;
1737 cur = dpriv->rx_current++%RX_RING_SIZE;
1738 rx_fd = dpriv->rx_fd + cur;
1747 dscc4_rx_skb(dpriv, dev);
1751 if (dpriv->flags & RdoSet)
1757 writel(dpriv->rx_fd_dma +
1758 (dpriv->rx_current%RX_RING_SIZE)*
1774 scc_patchl(0, RxActivate, dpriv, dev, CCR2);
1799 static struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv)
1805 int last = dpriv->tx_dirty%TX_RING_SIZE;
1806 struct TxFD *tx_fd = dpriv->tx_fd + last;
1812 tx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
1815 dpriv->tx_skbuff[last] = skb;
1822 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1823 struct pci_dev *pdev = dpriv->pci_priv->pdev;
1829 ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma);
1832 dpriv->rx_fd = rx_fd = (struct RxFD *) ring;
1834 ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma);
1837 dpriv->tx_fd = tx_fd = (struct TxFD *) ring;
1839 memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE);
1840 dpriv->tx_dirty = 0xffffffff;
1841 i = dpriv->tx_current = 0;
1845 tx_fd->data = cpu_to_le32(dpriv->tx_fd_dma);
1846 (tx_fd++)->next = cpu_to_le32(dpriv->tx_fd_dma +
1850 if (!dscc4_init_dummy_skb(dpriv))
1853 memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
1854 i = dpriv->rx_dirty = dpriv->rx_current = 0;
1861 if (try_get_rx_skb(dpriv, dev) >= 0)
1862 dpriv->rx_dirty++;
1863 (rx_fd++)->next = cpu_to_le32(dpriv->rx_fd_dma +
1870 pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma);
1872 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
1895 struct dscc4_dev_priv *dpriv = root + i;
1897 dscc4_release_ring(dpriv);
1899 dpriv->iqrx, dpriv->iqrx_dma);
1901 dpriv->iqtx, dpriv->iqtx_dma);
1917 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1933 dpriv->encoding = encoding;
1934 dpriv->parity = parity;