Lines Matching defs:tim_int_mask0
304 val64 = hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
305 hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX];
310 writeq(~val64, &hldev->common_reg->tim_int_mask0);
347 writeq(VXGE_HW_INTR_MASK_ALL, &hldev->common_reg->tim_int_mask0);
624 if ((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
625 (hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
626 writeq((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
627 hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX]),
2344 u64 tim_int_mask0[4] = {[0 ...3] = 0};
2349 VXGE_HW_DEVICE_TIM_INT_MASK_SET(tim_int_mask0,
2352 val64 = readq(&hldev->common_reg->tim_int_mask0);
2354 if ((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
2355 (tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
2356 writeq((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
2357 tim_int_mask0[VXGE_HW_VPATH_INTR_RX] | val64),
2358 &hldev->common_reg->tim_int_mask0);
2382 u64 tim_int_mask0[4] = {[0 ...3] = 0};
2387 VXGE_HW_DEVICE_TIM_INT_MASK_SET(tim_int_mask0,
2390 val64 = readq(&hldev->common_reg->tim_int_mask0);
2392 if ((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
2393 (tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
2394 writeq((~(tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
2395 tim_int_mask0[VXGE_HW_VPATH_INTR_RX])) & val64,
2396 &hldev->common_reg->tim_int_mask0);