Lines Matching refs:vp_reg
1292 ring->vp_reg = vp->vpath->vp_reg;
2354 fifo->vp_reg = vpath->vp_reg;
2509 struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
2516 writeq(val64, &vp_reg->pci_config_access_cfg1);
2519 &vp_reg->pci_config_access_cfg2);
2523 &vp_reg->pci_config_access_cfg2,
2529 val64 = readq(&vp_reg->pci_config_access_status);
2844 struct vxge_hw_vpath_reg __iomem *vp_reg;
2851 vp_reg = hldev->vpath_reg[hldev->first_vp_id];
2853 writeq(0, &vp_reg->rts_access_steer_ctrl);
2855 writeq(on_off, &vp_reg->rts_access_steer_data0);
2856 writeq(0, &vp_reg->rts_access_steer_data1);
2867 &vp_reg->rts_access_steer_ctrl,
2884 struct vxge_hw_vpath_reg __iomem *vp_reg;
2894 vp_reg = vpath->vp_reg;
2913 &vp_reg->rts_access_steer_ctrl,
2920 val64 = readq(&vp_reg->rts_access_steer_ctrl);
2924 *data1 = readq(&vp_reg->rts_access_steer_data0);
2930 *data2 = readq(&vp_reg->rts_access_steer_data1);
2950 struct vxge_hw_vpath_reg __iomem *vp_reg;
2958 vp_reg = vpath->vp_reg;
2960 writeq(data1, &vp_reg->rts_access_steer_data0);
2966 writeq(data2, &vp_reg->rts_access_steer_data1);
2976 &vp_reg->rts_access_steer_ctrl,
2983 val64 = readq(&vp_reg->rts_access_steer_ctrl);
3290 rxd_new_count = readl(&ring->vp_reg->prc_rxd_doorbell);
3291 rxd_spat = readq(&ring->vp_reg->prc_cfg6);
3416 struct vxge_hw_vpath_reg __iomem *vp_reg;
3419 vp_reg = vpath->vp_reg;
3425 val64 = readq(&vp_reg->prc_cfg1);
3427 writeq(val64, &vp_reg->prc_cfg1);
3429 val64 = readq(&vpath->vp_reg->prc_cfg6);
3431 writeq(val64, &vpath->vp_reg->prc_cfg6);
3433 val64 = readq(&vp_reg->prc_cfg7);
3456 writeq(val64, &vp_reg->prc_cfg7);
3460 vpath->ringh) >> 3), &vp_reg->prc_cfg5);
3462 val64 = readq(&vp_reg->prc_cfg4);
3474 writeq(val64, &vp_reg->prc_cfg4);
3489 struct vxge_hw_vpath_reg __iomem *vp_reg;
3492 vp_reg = vpath->vp_reg;
3493 status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg);
3498 val64 = readq(&vp_reg->kdfc_drbl_triplet_total);
3520 writeq(val64, &vp_reg->kdfc_fifo_trpl_partition);
3523 &vp_reg->kdfc_fifo_trpl_ctrl);
3525 val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl);
3537 writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);
3538 writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);
3562 struct vxge_hw_vpath_reg __iomem *vp_reg;
3565 vp_reg = vpath->vp_reg;
3569 vpath->vsport_number), &vp_reg->xmac_vsport_choice);
3573 val64 = readq(&vp_reg->xmac_rpa_vcfg);
3583 writeq(val64, &vp_reg->xmac_rpa_vcfg);
3584 val64 = readq(&vp_reg->rxmac_vcfg0);
3599 writeq(val64, &vp_reg->rxmac_vcfg0);
3601 val64 = readq(&vp_reg->rxmac_vcfg1);
3613 writeq(val64, &vp_reg->rxmac_vcfg1);
3629 struct vxge_hw_vpath_reg __iomem *vp_reg;
3633 vp_reg = vpath->vp_reg;
3636 writeq((u64)0, &vp_reg->tim_dest_addr);
3637 writeq((u64)0, &vp_reg->tim_vpath_map);
3638 writeq((u64)0, &vp_reg->tim_bitmap);
3639 writeq((u64)0, &vp_reg->tim_remap);
3644 VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn);
3646 val64 = readq(&vp_reg->tim_pci_cfg);
3648 writeq(val64, &vp_reg->tim_pci_cfg);
3652 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
3695 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
3696 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
3722 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
3723 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
3752 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
3757 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
3800 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
3801 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
3827 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
3828 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
3857 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
3861 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]);
3862 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]);
3863 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]);
3864 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]);
3865 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);
3866 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);
3875 struct vxge_hw_vpath_reg __iomem *vp_reg;
3880 vp_reg = vpath->vp_reg;
3884 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
3890 &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
3906 struct vxge_hw_vpath_reg __iomem *vp_reg;
3914 vp_reg = vpath->vp_reg;
3916 status = __vxge_hw_vpath_swapper_set(vpath->vp_reg);
3936 val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);
3957 writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl);
3986 vpath->vp_reg = hldev->vpath_reg[vp_id];
4066 val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
4071 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
4157 writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg);
4207 new_count = readq(&vpath->vp_reg->rxdmem_size);
4212 &vpath->vp_reg->prc_rxd_doorbell);
4213 readl(&vpath->vp_reg->prc_rxd_doorbell);
4216 val64 = readq(&vpath->vp_reg->prc_cfg6);
4353 &vpath->vp_reg->stats_cfg);
4417 struct vxge_hw_vpath_reg __iomem *vp_reg;
4424 vp_reg = vpath->vp_reg;
4431 &vp_reg->xmac_stats_access_cmd,
4436 *stat = readq(&vp_reg->xmac_stats_access_data);
4517 struct vxge_hw_vpath_reg __iomem *vp_reg;
4523 vp_reg = vpath->vp_reg;
4525 val64 = readq(&vp_reg->vpath_debug_stats0);
4529 val64 = readq(&vp_reg->vpath_debug_stats1);
4533 val64 = readq(&vp_reg->vpath_debug_stats2);
4537 val64 = readq(&vp_reg->vpath_debug_stats3);
4541 val64 = readq(&vp_reg->vpath_debug_stats4);
4545 val64 = readq(&vp_reg->vpath_debug_stats5);
4549 val64 = readq(&vp_reg->vpath_debug_stats6);
4553 val64 = readq(&vp_reg->vpath_genstats_count01);
4558 val64 = readq(&vp_reg->vpath_genstats_count01);
4563 val64 = readq(&vp_reg->vpath_genstats_count23);
4568 val64 = readq(&vp_reg->vpath_genstats_count01);
4573 val64 = readq(&vp_reg->vpath_genstats_count4);
4578 val64 = readq(&vp_reg->vpath_genstats_count5);
4609 val64 = readq(&vp_reg->rx_multi_cast_stats);
4613 val64 = readq(&vp_reg->rx_frm_transferred);
4617 val64 = readq(&vp_reg->rxd_returned);
4621 val64 = readq(&vp_reg->dbg_stats_rx_mpa);
4629 val64 = readq(&vp_reg->dbg_stats_rx_fau);
4637 val64 = readq(&vp_reg->tx_vp_reset_discarded_frms);