Lines Matching refs:ug_info
215 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
233 ugeth->ug_info->uf_info.max_rx_buf_length +
430 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
573 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
576 (ugeth->ug_info->bdRingLenTx[i] *
582 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
585 (ugeth->ug_info->bdRingLenRx[i] *
597 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num + 1);
687 switch (ugeth->ug_info->numThreadsTx) {
721 switch (ugeth->ug_info->numThreadsRx) {
923 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
955 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
979 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1022 if (ugeth->ug_info->rxExtendedFiltering) {
1025 if (ugeth->ug_info->largestexternallookupkeysize ==
1029 if (ugeth->ug_info->largestexternallookupkeysize ==
1040 ugeth->ug_info->riscTx, 0);
1045 ugeth->ug_info->riscRx, 1);
1334 struct ucc_geth_info *ug_info;
1343 ug_info = ugeth->ug_info;
1355 maccfg2 |= ug_info->padAndCrc;
1393 struct ucc_geth_info *ug_info = ugeth->ug_info;
1396 if (!ug_info->tbi_node)
1400 tbiphy = of_phy_find_device(ug_info->tbi_node);
1409 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1411 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1437 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1471 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1492 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1507 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1523 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1552 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1580 disable_irq(ugeth->ug_info->uf_info.irq);
1589 enable_irq(ugeth->ug_info->uf_info.irq);
1705 struct ucc_geth_info *ug_info = ugeth->ug_info;
1708 if (!ug_info->tbi_node) {
1714 tbiphy = of_phy_find_device(ug_info->tbi_node);
1743 struct ucc_geth_info *ug_info = priv->ug_info;
1750 phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1918 ugeth->ug_info->riscRx, 1);
1923 ugeth->ug_info->riscTx, 0);
1927 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1931 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1946 if (ugeth->ug_info->uf_info.bd_mem_part ==
1949 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1955 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1959 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1963 ugeth->ug_info->
1976 if (ugeth->ug_info->uf_info.bd_mem_part ==
1979 else if (ugeth->ug_info->uf_info.bd_mem_part ==
2076 struct ucc_geth_info *ug_info;
2080 ug_info = ugeth->ug_info;
2081 uf_info = &ug_info->uf_info;
2092 for (i = 0; i < ug_info->numQueuesRx; i++) {
2093 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2094 (ug_info->bdRingLenRx[i] %
2105 for (i = 0; i < ug_info->numQueuesTx; i++) {
2106 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2126 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2133 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2141 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2153 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2163 if (ug_info->cam && !ug_info->ecamptr) {
2170 if ((ug_info->numStationAddresses !=
2172 ug_info->rxExtendedFiltering) {
2181 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2182 for (i = 0; i < ug_info->numQueuesRx; i++)
2185 for (i = 0; i < ug_info->numQueuesTx; i++)
2198 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2199 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2219 struct ucc_geth_info *ug_info;
2236 ug_info = ugeth->ug_info;
2237 uf_info = &ug_info->uf_info;
2241 switch (ug_info->numThreadsRx) {
2265 switch (ug_info->numThreadsTx) {
2290 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2291 ug_info->ipAddressAlignment ||
2292 (ug_info->numStationAddresses !=
2296 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) ||
2297 (ug_info->vlanOperationNonTagged !=
2305 init_rx_parameters(ug_info->bro,
2306 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2313 init_flow_control_params(ug_info->aufc,
2314 ug_info->receiveFlowControl,
2315 ug_info->transmitFlowControl,
2316 ug_info->pausePeriod,
2317 ug_info->extensionField,
2325 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2326 ug_info->nonBackToBackIfgPart2,
2327 ug_info->
2329 ug_info->backToBackInterFrameGap,
2340 ret_val = init_half_duplex_params(ug_info->altBeb,
2341 ug_info->backPressureNoBackoff,
2342 ug_info->noBackoff,
2343 ug_info->excessDefer,
2344 ug_info->altBebTruncation,
2345 ug_info->maxRetransmission,
2346 ug_info->collisionWindow,
2366 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2371 for (j = 0; j < ug_info->numQueuesTx; j++) {
2375 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2378 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2410 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2411 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2415 for (j = 0; j < ug_info->numQueuesRx; j++) {
2416 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2446 for (j = 0; j < ug_info->numQueuesTx; j++) {
2449 ugeth->ug_info->bdRingLenTx[j],
2459 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2464 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2477 for (j = 0; j < ug_info->numQueuesRx; j++) {
2480 ugeth->ug_info->bdRingLenRx[j],
2490 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2495 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2553 ug_info->vtagtable[i]);
2558 ug_info->iphoffset[i]);
2563 qe_muram_alloc(ug_info->numQueuesTx *
2581 for (i = 0; i < ug_info->numQueuesTx; i++) {
2583 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2585 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2591 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2604 if (ug_info->numQueuesTx > 1) {
2627 ug_info->mblinterval);
2629 ug_info->nortsrbytetime);
2630 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2632 ug_info->strictpriorityq);
2633 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2634 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2637 ug_info->weightfactor[i]);
2652 if (ug_info->
2677 if (ug_info->numQueuesTx > 1)
2679 if (ug_info->ipCheckSumGenerate)
2681 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2733 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2736 if (ug_info->
2761 qe_muram_alloc(ug_info->numQueuesRx *
2779 for (i = 0; i < ug_info->numQueuesRx; i++) {
2782 ug_info->interruptcoalescingmaxvalue[i]);
2785 ug_info->interruptcoalescingmaxvalue[i]);
2792 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2794 init_min_frame_len(ug_info->minFrameLength,
2798 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2800 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2805 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2812 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
2817 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2820 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2823 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2828 qe_muram_alloc(ug_info->numQueuesRx *
2847 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2852 for (i = 0; i < ug_info->numQueuesRx; i++) {
2853 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2856 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2870 if (ug_info->rxExtendedFiltering)
2872 if (ug_info->dynamicMaxFrameLength)
2874 if (ug_info->dynamicMinFrameLength)
2877 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2879 ug_info->
2881 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2882 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2883 if (ug_info->ipCheckSumCheck)
2885 if (ug_info->ipAddressAlignment)
2892 init_firmware_statistics_gathering_mode((ug_info->
2895 (ug_info->statisticsMode &
2908 if (ug_info->rxExtendedFiltering) {
2909 if (!ug_info->extendedFilteringChainPointer) {
2935 (u32) ug_info->extendedFilteringChainPointer);
2992 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2994 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2997 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2998 if ((ug_info->largestexternallookupkeysize !=
3000 (ug_info->largestexternallookupkeysize !=
3002 (ug_info->largestexternallookupkeysize !=
3010 ug_info->largestexternallookupkeysize;
3012 if (ug_info->rxExtendedFiltering) {
3014 if (ug_info->largestexternallookupkeysize ==
3018 if (ug_info->largestexternallookupkeysize ==
3029 ug_info->riscRx, 1)) != 0) {
3037 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3044 ug_info->riscTx, 0)) != 0) {
3052 for (i = 0; i < ug_info->numQueuesRx; i++) {
3099 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3137 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3253 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3293 ugeth->ug_info->uf_info.max_rx_buf_length +
3302 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3322 struct ucc_geth_info *ug_info;
3325 ug_info = ugeth->ug_info;
3329 for (i = 0; i < ug_info->numQueuesTx; i++)
3334 for (i = 0; i < ug_info->numQueuesRx; i++)
3350 struct ucc_geth_info *ug_info;
3357 ug_info = ugeth->ug_info;
3394 int irq = ugeth->ug_info->uf_info.irq;
3520 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3555 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3741 struct ucc_geth_info *ug_info;
3775 ug_info = &ugeth_info[ucc_num];
3776 if (ug_info == NULL) {
3783 ug_info->uf_info.ucc_num = ucc_num;
3787 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3788 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3789 (ug_info->uf_info.rx_clock > QE_CLK24)) {
3808 ug_info->uf_info.rx_clock = *prop;
3813 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3814 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3815 (ug_info->uf_info.tx_clock > QE_CLK24)) {
3832 ug_info->uf_info.tx_clock = *prop;
3839 ug_info->uf_info.regs = res.start;
3840 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3842 ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0);
3845 ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3851 prop = of_get_property(ug_info->phy_node, "interface", NULL);
3881 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3882 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3883 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3884 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3885 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3886 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3887 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3894 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3896 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
3901 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3902 ug_info->uf_info.irq);
3920 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3949 ugeth->ug_info = ug_info;