Lines Matching refs:csr5
511 int csr5;
528 csr5 = ioread32(ioaddr + CSR5);
533 if ((csr5 & (NormalIntr|AbnormalIntr)) == 0)
542 if (!rxd && (csr5 & (RxIntr | RxNoBuf))) {
548 if (!(csr5&~(AbnormalIntr|NormalIntr|RxPollInt|TPLnkPass)))
555 iowrite32(csr5 & 0x0001ff3f, ioaddr + CSR5);
559 iowrite32(csr5 & 0x0001ffff, ioaddr + CSR5);
562 if (csr5 & (RxIntr | RxNoBuf)) {
570 printk(KERN_DEBUG "%s: interrupt csr5=%#8.8x new csr5=%#8.8x\n",
571 dev->name, csr5, ioread32(ioaddr + CSR5));
574 if (csr5 & (TxNoBuf | TxDied | TxIntr | TimerInt)) {
643 if (csr5 & TxDied) {
647 csr5, ioread32(ioaddr + CSR6),
655 if (csr5 & AbnormalIntr) { /* Abnormal error summary bit. */
656 if (csr5 == 0xffffffff)
658 if (csr5 & TxJabber) tp->stats.tx_errors++;
659 if (csr5 & TxFIFOUnderflow) {
668 if (csr5 & (RxDied | RxNoBuf)) {
674 if (csr5 & RxDied) { /* Missed a Rx frame. */
683 if (csr5 & (TPLnkPass | TPLnkFail | 0x08000000)) {
685 (tp->link_change)(dev, csr5);
687 if (csr5 & SystemError) {
688 int error = (csr5 >> 23) & 7;
707 if (csr5 & TimerInt) {
712 csr5);
719 dev_warn(&dev->dev, "Too much work during an interrupt, csr5=0x%08x. (%lu) (%d,%d,%d)\n",
720 csr5, tp->nir, tx, rx, oi);
735 iowrite32(((~csr5) & 0x0001ebef) | AbnormalIntr | TimerInt, ioaddr + CSR7);
745 csr5 = ioread32(ioaddr + CSR5);
749 csr5 &= ~RxPollInt;
750 } while ((csr5 & (TxNoBuf |
761 } while ((csr5 & (NormalIntr|AbnormalIntr)) != 0);
796 printk(KERN_DEBUG "%s: exiting interrupt, csr5=%#04x\n",