Lines Matching refs:sisr
922 u32 sisr;
926 * Read sisr but don't reset it yet.
930 sisr=readl(olympic_mmio+SISR) ;
931 if (!(sisr & SISR_MI)) /* Interrupt isn't for us */
933 sisr=readl(olympic_mmio+SISR_RR) ; /* Read & Reset sisr */
938 if (sisr == 0xffffffff) {
944 if (sisr & (SISR_SRB_REPLY | SISR_TX1_EOF | SISR_RX_STATUS | SISR_ADAPTER_CHECK |
949 if((sisr & SISR_ERR) && (readl(olympic_mmio+EISR) & EISR_MASK_OPTIONS)) {
959 if(sisr & SISR_SRB_REPLY) {
970 if (sisr & SISR_TX1_EOF) {
987 if (sisr & SISR_RX_STATUS) {
991 if (sisr & SISR_ADAPTER_CHECK) {
1001 if (sisr & SISR_ASB_FREE) {
1008 if (sisr & SISR_ARB_CMD) {
1012 if (sisr & SISR_TRB_REPLY) {
1020 if (sisr & SISR_RX_NOBUF) {
1025 printk(KERN_WARNING "%s: Unexpected interrupt: %x\n",dev->name, sisr);