Lines Matching refs:xl_mmio
163 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
175 printk("DNLISTPTR = %04x\n", readl(xl_mmio + MMIO_DNLISTPTR) );
177 printk("DmaCtl = %04x\n", readl(xl_mmio + MMIO_DMA_CTRL) );
186 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
198 printk("UPLISTPTR = %04x\n", readl(xl_mmio + MMIO_UPLISTPTR));
200 printk("DmaCtl = %04x\n", readl(xl_mmio + MMIO_DMA_CTRL));
219 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
222 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
223 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
226 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
227 writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
230 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
231 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
234 writel(IO_WORD_WRITE | EECONTROL , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
235 writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
238 writel(IO_WORD_READ | EEDATA , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
239 return readw(xl_mmio + MMIO_MACDATA) ;
251 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
254 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
255 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
258 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
259 writew(EE_ENABLE_WRITE, xl_mmio + MMIO_MACDATA) ;
262 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
263 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
266 writel(IO_WORD_WRITE | EEDATA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
267 writew(ee_value, xl_mmio + MMIO_MACDATA) ;
270 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
271 writew(EEWRITE + ee_addr, xl_mmio + MMIO_MACDATA) ;
274 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
275 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
330 xl_priv->xl_mmio=ioremap(pci_resource_start(pdev,1), XL_IO_SPACE);
345 iounmap(xl_priv->xl_mmio) ;
358 iounmap(xl_priv->xl_mmio) ;
396 xl_priv->xl_card_name, (unsigned int)dev->base_addr ,xl_priv->xl_mmio, dev->irq);
416 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
432 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
440 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
452 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
453 result_8 = readb(xl_mmio + MMIO_MACDATA) ;
455 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
456 writeb(result_8, xl_mmio + MMIO_MACDATA) ;
463 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
466 printk(KERN_INFO "Read from PMBAR = %04x\n", readw(xl_mmio + MMIO_MACDATA));
469 if ( readw( (xl_mmio + MMIO_MACDATA)) & PMB_CPHOLD ) {
473 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
474 result_16 = readw(xl_mmio + MMIO_MACDATA) ;
476 writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
477 writew(result_16,xl_mmio + MMIO_MACDATA) ;
481 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
482 result_8 = readb(xl_mmio + MMIO_MACDATA) ;
484 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
485 writeb(result_8, xl_mmio + MMIO_MACDATA) ;
501 xl_mmio + MMIO_MAC_ACCESS_CMD);
502 writeb(xl_priv->fw->data[j], xl_mmio + MMIO_MACDATA);
510 xl_mmio + MMIO_MAC_ACCESS_CMD);
512 xl_mmio + MMIO_MACDATA);
521 writel(MEM_WORD_WRITE | 0xDFFF4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
522 writew(start >> 4, xl_mmio + MMIO_MACDATA);
526 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
527 result_8 = readb(xl_mmio + MMIO_MACDATA) ;
529 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
530 writeb(result_8, xl_mmio + MMIO_MACDATA) ;
534 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
535 result_16 = readw(xl_mmio + MMIO_MACDATA) ;
537 writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
538 writew(result_16,xl_mmio + MMIO_MACDATA) ;
553 writew(SETINDENABLE | 0xFFF, xl_mmio + MMIO_COMMAND) ;
556 while ( !(readw(xl_mmio + MMIO_INTSTATUS_AUTO) & INTSTAT_SRB) ) {
570 writel(MMIO_WORD_WRITE | RXBUFAREA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
571 writew(0xD000, xl_mmio + MMIO_MACDATA) ;
573 writel(MMIO_WORD_WRITE | RXEARLYTHRESH, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
574 writew(0X0020, xl_mmio + MMIO_MACDATA) ;
576 writew( SETTXSTARTTHRESH | 0x40 , xl_mmio + MMIO_COMMAND) ;
578 writeb(0x04, xl_mmio + MMIO_DNBURSTTHRESH) ;
579 writeb(0x04, xl_mmio + DNPRIREQTHRESH) ;
586 writel(MMIO_BYTE_READ | WRBR, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
587 xl_priv->srb = readb(xl_mmio + MMIO_MACDATA) << 8 ;
588 writel( (MMIO_BYTE_READ | WRBR) + 1, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
589 xl_priv->srb = xl_priv->srb | readb(xl_mmio + MMIO_MACDATA) ;
592 writel(IO_WORD_READ | SWITCHSETTINGS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
593 if ( readw(xl_mmio + MMIO_MACDATA) & 2) {
607 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
721 writel(xl_priv->rx_ring_dma_addr, xl_mmio + MMIO_UPLISTPTR) ;
740 writel(xl_priv->tx_ring_dma_addr, xl_mmio + MMIO_DNLISTPTR) ;
741 writel(DNUNSTALL, xl_mmio + MMIO_COMMAND) ;
742 writel(UPUNSTALL, xl_mmio + MMIO_COMMAND) ;
743 writel(DNENABLE, xl_mmio + MMIO_COMMAND) ;
744 writeb(0x40, xl_mmio + MMIO_DNPOLL) ;
750 writel(SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
751 writel(SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
761 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
773 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
774 writeb(OPEN_NIC, xl_mmio + MMIO_MACDATA) ;
780 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb)+ 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
781 writeb(0xff,xl_mmio + MMIO_MACDATA) ;
784 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
785 writeb(0x00, xl_mmio + MMIO_MACDATA) ;
786 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 9, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
787 writeb(0x00, xl_mmio + MMIO_MACDATA) ;
796 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
797 writeb(xl_priv->xl_laa[i-10],xl_mmio + MMIO_MACDATA) ;
802 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
803 writeb(dev->dev_addr[i-10], xl_mmio + MMIO_MACDATA) ;
809 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
810 writeb(0x00,xl_mmio + MMIO_MACDATA) ;
818 writel(MEM_BYTE_WRITE | MF_CSRB, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
819 writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
820 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
821 writeb(MISR_CSRB , xl_mmio + MMIO_MACDATA) ;
828 while (! (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
840 writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb)+2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
841 if (readb(xl_mmio + MMIO_MACDATA)!=0) {
842 open_err = readb(xl_mmio + MMIO_MACDATA) << 8 ;
843 writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb) + 7, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
844 open_err |= readb(xl_mmio + MMIO_MACDATA) ;
847 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
848 xl_priv->asb = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
851 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 10, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
852 printk(", SRB: %04x",swab16(readw(xl_mmio + MMIO_MACDATA)) ) ;
854 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 12, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
855 xl_priv->arb = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
857 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 14, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
858 vsoff = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
866 writel( (MEM_BYTE_READ | 0xD0000 | vsoff) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
867 ver_str[i] = readb(xl_mmio + MMIO_MACDATA) ;
876 writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
924 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
962 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
997 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
1018 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
1030 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1033 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
1041 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1077 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1080 intstatus = readw(xl_mmio + MMIO_INTSTATUS) ;
1094 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1107 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
1113 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1119 writel(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1125 writel(DNRESET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1126 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { /* Wait for command to run */
1132 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1145 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
1156 writel(MMIO_WORD_READ | MACSTATUS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1157 macstatus = readw(xl_mmio + MMIO_MACDATA) ;
1173 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1179 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1185 writel( SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
1186 writel( SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
1237 /* readl(xl_mmio + MMIO_DNLISTPTR) ; */
1260 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1284 writel(ACK_INTERRUPT | DNCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
1296 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1305 writew(DNSTALL, xl_mmio + MMIO_COMMAND) ;
1307 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1314 writew(DNDISABLE, xl_mmio + MMIO_COMMAND) ;
1316 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1323 writew(UPSTALL, xl_mmio + MMIO_COMMAND) ;
1325 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1337 writel(SETINTENABLE, xl_mmio + MMIO_COMMAND) ;
1342 while (!(readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
1351 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD);
1352 if (readb(xl_mmio + MMIO_MACDATA) != CLOSE_NIC) {
1355 writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1356 if (readb(xl_mmio + MMIO_MACDATA)==0) {
1358 writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1363 printk(KERN_INFO "%s: Close nic command returned error code %02x\n",dev->name, readb(xl_mmio + MMIO_MACDATA)) ;
1369 writew(UPRESET, xl_mmio + MMIO_COMMAND) ;
1371 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1378 writew(DNRESET, xl_mmio + MMIO_COMMAND) ;
1380 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1434 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1438 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1439 srb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
1440 writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1441 ret_code = readb(xl_mmio + MMIO_MACDATA) ;
1467 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1469 printk("%02x:",readb(xl_mmio + MMIO_MACDATA)) ;
1525 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1529 writel( ( MEM_BYTE_READ | 0xD0000 | xl_priv->arb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1530 arb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
1533 writel( ( (MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1535 printk(KERN_INFO "%s: Ring Status Change: New Status = %04x\n", dev->name, swab16(readw(xl_mmio + MMIO_MACDATA) )) ;
1537 lan_status = swab16(readw(xl_mmio + MMIO_MACDATA));
1540 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1600 writel( ((MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1601 xl_priv->mac_buffer = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
1611 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1616 writel( ((MEM_BYTE_READ | 0xD0000 | xl_priv->asb) + 2), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1617 if (readb(xl_mmio + MMIO_MACDATA) != 0xff) {
1622 writel(MEM_BYTE_WRITE | MF_ASBFR, xl_mmio + MMIO_MAC_ACCESS_CMD);
1623 writeb(0xff, xl_mmio + MMIO_MACDATA) ;
1624 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1625 writeb(MISR_ASBFR, xl_mmio + MMIO_MACDATA) ;
1638 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
1652 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1655 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
1657 writel(MEM_BYTE_WRITE | 0xd0000 | xl_priv->asb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1658 writeb(0x81, xl_mmio + MMIO_MACDATA) ;
1660 writel(MEM_WORD_WRITE | 0xd0000 | xl_priv->asb | 6, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1661 writew(swab16(xl_priv->mac_buffer), xl_mmio + MMIO_MACDATA) ;
1665 writel(MEM_BYTE_WRITE | MF_RASB, xl_mmio + MMIO_MAC_ACCESS_CMD);
1666 writeb(0xff, xl_mmio + MMIO_MACDATA) ;
1668 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1669 writeb(MISR_RASB, xl_mmio + MMIO_MACDATA) ;
1683 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1686 writel(MMIO_BYTE_READ | 0xd0000 | xl_priv->asb | 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1687 ret_code = readb(xl_mmio + MMIO_MACDATA) ;
1700 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
1711 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1715 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1716 writeb(READ_LOG, xl_mmio + MMIO_MACDATA) ;
1720 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1721 writeb(CLOSE_NIC, xl_mmio + MMIO_MACDATA) ;
1725 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1726 writeb(SET_RECEIVE_MODE, xl_mmio + MMIO_MACDATA) ;
1727 writel(MEM_WORD_WRITE | 0xD0000 | xl_priv->srb | 4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1728 writew(xl_priv->xl_copy_all_options, xl_mmio + MMIO_MACDATA) ;
1732 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1733 writeb(SET_FUNC_ADDRESS, xl_mmio + MMIO_MACDATA) ;
1734 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 6 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1735 writeb(xl_priv->xl_functional_addr[0], xl_mmio + MMIO_MACDATA) ;
1736 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 7 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1737 writeb(xl_priv->xl_functional_addr[1], xl_mmio + MMIO_MACDATA) ;
1738 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 8 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1739 writeb(xl_priv->xl_functional_addr[2], xl_mmio + MMIO_MACDATA) ;
1740 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 9 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1741 writeb(xl_priv->xl_functional_addr[3], xl_mmio + MMIO_MACDATA) ;
1749 writel(MEM_BYTE_WRITE | MF_CSRB , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1750 writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
1752 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1753 writeb(MISR_CSRB, xl_mmio + MMIO_MACDATA) ;
1768 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1772 writel(MMIO_BYTE_READ | MISR_RW, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1773 if (readb(xl_mmio + MMIO_MACDATA) != 0) { /* Misr not clear */
1775 writel(MEM_BYTE_READ | 0xDFFE0 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1776 while (readb(xl_mmio + MMIO_MACDATA) != 0 ) {} ; /* Empty Loop */
1780 writel(MMIO_BYTE_WRITE | MISR_AND, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1781 writeb(0x80, xl_mmio + MMIO_MACDATA) ;
1818 iounmap(xl_priv->xl_mmio) ;