Lines Matching refs:reg_data
170 unsigned int reg_data = 0, phy_reg;
208 reg_data = TITAN_GE_READ(TITAN_GE_GMII_CONFIG_GENERAL +
210 reg_data |= 0x3;
212 (port_num << 12)), reg_data);
220 unsigned long reg_data;
222 reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12));
223 if (!(reg_data & 0x8000)) {
226 reg_data |= 0x0001; /* Enable TMAC */
227 reg_data |= 0x4000; /* CRC Check Enable */
228 reg_data |= 0x2000; /* Padding enable */
229 reg_data |= 0x0800; /* CRC Add enable */
230 reg_data |= 0x0080; /* PAUSE frame */
233 (port_num << 12)), reg_data);
258 volatile unsigned long reg_data = 0;
286 reg_data = 0x9; /* Forward Enable Bit */
288 (port << 12)), reg_data);
377 unsigned int reg_data;
501 TITAN_GE_MDIO_PHY_IS, ®_data);
503 if (reg_data & 0x0400) {
506 TITAN_GE_MDIO_PHY_STATUS, ®_data);
507 if (!(reg_data & 0x0400)) {
535 unsigned long reg_data;
537 reg_data = TITAN_GE_READ(TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 +
541 reg_data |= 0x2;
544 reg_data |= 0x01;
545 reg_data |= 0x400; /* Use the 64-bit Multicast Hash bin */
548 reg_data = 0x2;
552 (port_num << 12)), reg_data);
553 if (reg_data & 0x01) {
660 unsigned long reg_data;
665 reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
666 reg_data |= 0x80000000;
667 TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
671 reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
672 reg_data &= ~(0xc0000000);
673 TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
676 reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
677 reg_data |= 0x00080000;
678 TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
682 reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
683 reg_data &= ~(0x000c0000);
684 TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
695 volatile unsigned long reg_data, reg_data1;
701 reg_data = TITAN_GE_READ(0x0004);
702 reg_data |= 0x100;
703 TITAN_GE_WRITE(0x0004, reg_data);
705 reg_data &= ~(0x100);
706 TITAN_GE_WRITE(0x0004, reg_data);
709 reg_data = TITAN_GE_READ(TITAN_GE_TSB_CTRL_1);
710 reg_data |= 0x00000700;
711 reg_data &= ~(0x00800000); /* Fencing */
715 TITAN_GE_WRITE(TITAN_GE_TSB_CTRL_1, reg_data);
735 reg_data = TITAN_GE_READ(TITAN_GE_XDMA_CONFIG);
736 reg_data &= ~(0x80000000); /* clear reset */
737 reg_data |= 0x1 << 29; /* sparse tx descriptor spacing */
738 reg_data |= 0x1 << 28; /* sparse rx descriptor spacing */
739 reg_data |= (0x1 << 23) | (0x1 << 24); /* Descriptor Coherency */
740 reg_data |= (0x1 << 21) | (0x1 << 22); /* Data Coherency */
741 TITAN_GE_WRITE(TITAN_GE_XDMA_CONFIG, reg_data);
745 reg_data = TITAN_GE_READ(TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8));
746 reg_data |= 0x80068000; /* No Rx_OOD */
747 TITAN_GE_WRITE((TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8)), reg_data);
750 reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG + (port_num << 8));
751 reg_data &= 0x4fffffff; /* Clear tx reset */
752 reg_data &= 0xfff4ffff; /* Clear rx reset */
755 reg_data |= 0xa0 | 0x30030000;
757 reg_data |= 0x40 | 0x20030000;
761 reg_data &= ~(0x10);
762 reg_data |= 0x0f; /* All of the packet */
765 TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG + (port_num << 8)), reg_data);
778 reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL);
779 reg_data = 0x1;
780 TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
781 reg_data &= ~(0x1);
782 TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
783 reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL);
784 TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
786 reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL);
787 reg_data = 0x1;
788 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
789 reg_data &= ~(0x1);
790 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
791 reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL);
792 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
798 reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_0);
800 reg_data |= 0x100000;
801 reg_data |= (0xff << 10);
803 TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
811 reg_data &= ~(0x00100000);
812 reg_data |= 0x200000;
814 TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
816 reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_0);
817 reg_data |= 0x100000;
819 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
821 reg_data |= (0xff << 10);
823 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
833 reg_data &= ~(0x00100000);
834 reg_data |= 0x200000;
836 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
841 reg_data = TITAN_GE_READ(0x4870);
843 reg_data |= 0x100000;
844 reg_data |= (0xff << 10) | (0xff + 1);
846 TITAN_GE_WRITE(0x4870, reg_data);
854 reg_data &= ~(0x00100000);
855 reg_data |= 0x200000;
857 TITAN_GE_WRITE(0x4870, reg_data);
859 reg_data = TITAN_GE_READ(0x494c);
860 reg_data |= 0x100000;
862 TITAN_GE_WRITE(0x494c, reg_data);
863 reg_data |= (0xff << 10) | (0xff + 1);
864 TITAN_GE_WRITE(0x494c, reg_data);
874 reg_data &= ~(0x00100000);
875 reg_data |= 0x200000;
877 TITAN_GE_WRITE(0x494c, reg_data);
887 reg_data = TITAN_GE_READ(0x48a0);
889 reg_data |= 0x100000;
890 reg_data |= (0xff << 10) | (2*(0xff + 1));
892 TITAN_GE_WRITE(0x48a0, reg_data);
900 reg_data &= ~(0x00100000);
901 reg_data |= 0x200000;
903 TITAN_GE_WRITE(0x48a0, reg_data);
905 reg_data = TITAN_GE_READ(0x4958);
906 reg_data |= 0x100000;
908 TITAN_GE_WRITE(0x4958, reg_data);
909 reg_data |= (0xff << 10) | (2*(0xff + 1));
910 TITAN_GE_WRITE(0x4958, reg_data);
920 reg_data &= ~(0x00100000);
921 reg_data |= 0x200000;
923 TITAN_GE_WRITE(0x4958, reg_data);
927 reg_data = TITAN_GE_READ(0x48a0);
929 reg_data |= 0x100000;
930 reg_data |= (0xff << 10) | (2*(0xff + 1));
932 TITAN_GE_WRITE(0x48a0, reg_data);
940 reg_data &= ~(0x00100000);
941 reg_data |= 0x200000;
943 TITAN_GE_WRITE(0x48a0, reg_data);
945 reg_data = TITAN_GE_READ(0x4958);
946 reg_data |= 0x100000;
948 TITAN_GE_WRITE(0x4958, reg_data);
949 reg_data |= (0xff << 10) | (2*(0xff + 1));
950 TITAN_GE_WRITE(0x4958, reg_data);
960 reg_data &= ~(0x00100000);
961 reg_data |= 0x200000;
963 TITAN_GE_WRITE(0x4958, reg_data);
969 reg_data = TITAN_GE_READ(TITAN_GE_TRTG_CONFIG + (port_num << 12));
992 reg_data |= 0x0001;
993 TITAN_GE_WRITE((TITAN_GE_TRTG_CONFIG + (port_num << 12)), reg_data);
1002 reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12));
1003 reg_data |= 0x0001; /* Enable TMAC */
1004 reg_data |= 0x6c70; /* PAUSE also set */
1006 TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + (port_num << 12)), reg_data);
1011 reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_2 + (port_num << 12));
1012 reg_data |= 0x218; /* DA_DROP bit and pause */
1013 TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_2 + (port_num << 12)), reg_data);
1021 reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12));
1022 reg_data |= 0x0001; /* RMAC Enable */
1023 reg_data |= 0x0010; /* CRC Check enable */
1024 reg_data |= 0x0040; /* Min Frame check enable */
1025 reg_data |= 0x4400; /* Max Frame check enable */
1027 TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data);
1061 reg_data = TITAN_GE_READ(0x1038 + (port_num << 12));
1062 reg_data &= ~(0x00f00000);
1063 TITAN_GE_WRITE((0x1038 + (port_num << 12)), reg_data);
1117 unsigned long reg_data;
1122 reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12));
1123 reg_data &= ~(0x00000001);
1124 TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data);
1429 unsigned long reg_data = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
1432 reg_data |= 0x3;
1434 reg_data |= 0x300;
1436 reg_data |= 0x30000;
1439 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data);
1546 unsigned long reg_data;
1549 reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG +
1551 reg_data |= 0xc0000000;
1553 (port_num << 8)), reg_data);
1556 reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 +
1558 reg_data &= ~(0x00000001);
1560 (port_num << 12)), reg_data);
1593 unsigned long reg_data;
1596 reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG +
1598 reg_data |= 0x000c0000;
1600 (port_num << 8)), reg_data);
1603 reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 +
1605 reg_data &= ~(0x00000001);
1607 (port_num << 12)), reg_data);
1887 unsigned int reg_data;
1890 reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 +
1892 reg_data &= ~(0x0001);
1894 (port_num << 12)), reg_data);
1897 reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 +
1899 reg_data &= ~(0x0001);
1901 (port_num << 12)), reg_data);