Lines Matching refs:TITAN_GE_WRITE
189 TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
193 TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
200 TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
204 TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE +
211 TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_GENERAL +
232 TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
264 TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port << 12)),
266 TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port << 12)),
268 TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port << 12)),
271 TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port << 12)),
273 TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port << 12)),
275 TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port << 12)),
278 TITAN_GE_WRITE((0x112c | (port << 12)), 0x1);
282 TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_2 +
287 TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_0 +
291 TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_LOW + (port << 12)),
293 TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_MID + (port << 12)),
295 TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_HIGH + (port << 12)),
299 TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_VID +
465 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, ack);
489 TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT +
551 TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 +
554 TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_LOW +
556 TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDLOW +
558 TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDHI +
560 TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_HI +
667 TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
673 TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
678 TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
684 TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
703 TITAN_GE_WRITE(0x0004, reg_data);
706 TITAN_GE_WRITE(0x0004, reg_data);
713 TITAN_GE_WRITE(0x000c, 0x00001100);
715 TITAN_GE_WRITE(TITAN_GE_TSB_CTRL_1, reg_data);
718 TITAN_GE_WRITE(0x00f8, 0x8);
721 TITAN_GE_WRITE(0x0068, 0x4);
728 TITAN_GE_WRITE((TITAN_GE_CHANNEL0_TX_DESC + (port_num << 8)),
730 TITAN_GE_WRITE((TITAN_GE_CHANNEL0_RX_DESC + (port_num << 8)),
741 TITAN_GE_WRITE(TITAN_GE_XDMA_CONFIG, reg_data);
747 TITAN_GE_WRITE((TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8)), reg_data);
765 TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG + (port_num << 8)), reg_data);
769 TITAN_GE_WRITE((0x5048 + (port_num << 8)), count);
780 TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
782 TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
784 TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
788 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
790 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
792 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
803 TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
809 TITAN_GE_WRITE(0x4844, reg_data1);
814 TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
819 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
823 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
831 TITAN_GE_WRITE(0x4944, reg_data1);
836 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
846 TITAN_GE_WRITE(0x4870, reg_data);
852 TITAN_GE_WRITE(0x4874, reg_data1);
857 TITAN_GE_WRITE(0x4870, reg_data);
862 TITAN_GE_WRITE(0x494c, reg_data);
864 TITAN_GE_WRITE(0x494c, reg_data);
872 TITAN_GE_WRITE(0x4950, reg_data1);
877 TITAN_GE_WRITE(0x494c, reg_data);
892 TITAN_GE_WRITE(0x48a0, reg_data);
898 TITAN_GE_WRITE(0x48a4, reg_data1);
903 TITAN_GE_WRITE(0x48a0, reg_data);
908 TITAN_GE_WRITE(0x4958, reg_data);
910 TITAN_GE_WRITE(0x4958, reg_data);
918 TITAN_GE_WRITE(0x495c, reg_data1);
923 TITAN_GE_WRITE(0x4958, reg_data);
932 TITAN_GE_WRITE(0x48a0, reg_data);
938 TITAN_GE_WRITE(0x48a4, reg_data1);
943 TITAN_GE_WRITE(0x48a0, reg_data);
948 TITAN_GE_WRITE(0x4958, reg_data);
950 TITAN_GE_WRITE(0x4958, reg_data);
958 TITAN_GE_WRITE(0x495c, reg_data1);
963 TITAN_GE_WRITE(0x4958, reg_data);
980 TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
983 TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
988 TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
993 TITAN_GE_WRITE((TITAN_GE_TRTG_CONFIG + (port_num << 12)), reg_data);
998 TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_2 + (port_num << 12)), 0xe197);
1000 TITAN_GE_WRITE((0x1258 + (port_num << 12)), 0x4000);
1006 TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + (port_num << 12)), reg_data);
1013 TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_2 + (port_num << 12)), reg_data);
1015 TITAN_GE_WRITE((0x1218 + (port_num << 12)), 0x3);
1018 TITAN_GE_WRITE((0x1208 + (port_num << 12)), 0x4000);
1027 TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data);
1039 TITAN_GE_WRITE(0x0038, 0x003);
1041 TITAN_GE_WRITE(0x0038, 0x303);
1052 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data1);
1053 TITAN_GE_WRITE(0x003c, 0x300);
1056 TITAN_GE_WRITE(0x0024, 0x04000024); /* IRQ vector */
1057 TITAN_GE_WRITE(0x0020, 0x000fb000); /* INTMSG base */
1063 TITAN_GE_WRITE((0x1038 + (port_num << 12)), reg_data);
1069 TITAN_GE_WRITE(0x1a80, 0);
1099 TITAN_GE_WRITE((0x5044 + (port_num << 8)), 0x1);
1124 TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data);
1127 TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT + (port_num << 8)), 0x0);
1130 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0);
1131 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_B, 0);
1405 TITAN_GE_WRITE((0x5048 + (port_num << 8)), ack);
1439 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data);
1464 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x3);
1466 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x300);
1468 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x30000);
1552 TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG +
1559 TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
1599 TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG +
1606 TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 +
1647 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, 0x0);
1672 TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port_num << 12)),
1674 TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port_num << 12)),
1676 TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port_num << 12)),
1679 TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port_num << 12)),
1681 TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port_num << 12)),
1683 TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port_num << 12)),
1893 TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
1900 TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 +
1942 TITAN_GE_WRITE(TITAN_GE_INT_COALESCING, delay);
1943 TITAN_GE_WRITE(0x5038, delay);