Lines Matching refs:tw32_f
518 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
538 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
539 tw32_f(TG3PCI_MEM_WIN_DATA, val);
542 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
565 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
569 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
823 tw32_f(MAC_MI_MODE,
836 tw32_f(MAC_MI_COM, frame_val);
858 tw32_f(MAC_MI_MODE, tp->mi_mode);
876 tw32_f(MAC_MI_MODE,
888 tw32_f(MAC_MI_COM, frame_val);
907 tw32_f(MAC_MI_MODE, tp->mi_mode);
1064 tw32_f(MAC_MI_MODE, tp->mi_mode);
1195 tw32_f(GRC_RX_CPU_EVENT, val);
1383 tw32_f(MAC_RX_MODE, tp->rx_mode);
1391 tw32_f(MAC_TX_MODE, tp->tx_mode);
1438 tw32_f(MAC_MODE, tp->mac_mode);
1917 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1970 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2206 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2254 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2290 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2678 tw32_f(MAC_MODE, mac_mode);
2681 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
3058 tw32_f(MAC_STATUS,
3066 tw32_f(MAC_MI_MODE,
3267 tw32_f(MAC_MI_MODE, tp->mi_mode);
3271 tw32_f(MAC_MODE, tp->mac_mode);
3276 tw32_f(MAC_EVENT, 0);
3278 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3288 tw32_f(MAC_STATUS,
3471 tw32_f(MAC_MODE, tp->mac_mode);
3500 tw32_f(MAC_MODE, tp->mac_mode);
3515 tw32_f(MAC_MODE, tp->mac_mode);
3601 tw32_f(MAC_MODE, tp->mac_mode);
3649 tw32_f(MAC_TX_AUTO_NEG, 0);
3652 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3655 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3672 tw32_f(MAC_MODE, tp->mac_mode);
3770 tw32_f(MAC_SERDES_CFG, val);
3773 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3803 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3804 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3806 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3845 tw32_f(MAC_SERDES_CFG, val);
3848 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3906 tw32_f(MAC_STATUS,
3927 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3930 tw32_f(MAC_MODE, tp->mac_mode);
3961 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3967 tw32_f(MAC_TX_AUTO_NEG, 0);
3971 tw32_f(MAC_MODE, tp->mac_mode);
3978 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3994 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4008 tw32_f(MAC_MODE, (tp->mac_mode |
4011 tw32_f(MAC_MODE, tp->mac_mode);
4055 tw32_f(MAC_MODE, tp->mac_mode);
4060 tw32_f(MAC_STATUS,
4109 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4198 tw32_f(MAC_MODE, tp->mac_mode);
4201 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4812 tw32_f(MAC_STATUS,
4989 tw32_f(HOSTCC_MODE, tp->coal_now);
6485 tw32_f(ofs, val);
6512 tw32_f(MAC_RX_MODE, tp->rx_mode);
6531 tw32_f(MAC_MODE, tp->mac_mode);
6535 tw32_f(MAC_TX_MODE, tp->tx_mode);
7040 tw32_f(MAC_MODE, tp->mac_mode);
7043 tw32_f(MAC_MODE, tp->mac_mode);
7048 tw32_f(MAC_MODE, tp->mac_mode);
7050 tw32_f(MAC_MODE, 0);
7157 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7265 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7272 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7282 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7330 tw32_f(cpu_base + CPU_PC, info.fw_base);
7337 tw32_f(cpu_base + CPU_PC, info.fw_base);
7347 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7700 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8048 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8062 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8093 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8103 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8135 tw32_f(WDMAC_MODE, val);
8154 tw32_f(RDMAC_MODE, rdmac_mode);
8195 tw32_f(MAC_TX_MODE, tp->tx_mode);
8238 tw32_f(MAC_RX_MODE, tp->rx_mode);
8245 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8248 tw32_f(MAC_RX_MODE, tp->rx_mode);
8272 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8502 tw32_f(MAC_MODE,
8506 tw32_f(MAC_MODE, tp->mac_mode);
8621 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9306 tw32_f(MAC_RX_MODE, rx_mode);
10638 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10640 tw32_f(MAC_RX_MODE, tp->rx_mode);
10678 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10699 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11586 tw32_f(GRC_EEPROM_ADDR,
11594 tw32_f(GRC_LOCAL_CTRL,
11850 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11890 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
13530 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13771 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13776 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);